Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Koji Horisaki

Kazumi Sato

Minoru Namekata

Masahiro Sekiya

Tomoko Adachi

Kiyoshi Toshimitsu

Ryo Yamaki

Youyang Ng

Gibeom Park

Kazuhisa Horiuchi

Shinichi Kanno

Toshikatsu Hida

Osamu Torii

Toshiyuki Yamagishi

Masahiro Takagi

Hiroshi Tsurumi

Takashi Nakada

Kojiro Suzuki

Yasuo Akatsuka

Toshihiro Nakamura

Dong Zhang

Jun Deguchi

Ichiro Seto

Takashi Ueno

Hideaki Majima

Akira Yamaga

Yuki Fujimura

Kiyotaka Matsue

Nau Ozaki

Hideki Yamada

A memory system includes a non-volatile memory having a plurality of memory cells and a memory controller. The memory controller is configured to generate a histogram indicating, with respect to each of a plurality of threshold voltage levels for multi-level cell (MLC) reading, a number of memory cells at the threshold voltage level, based on data read from the plurality of memory cells using a plurality of reference read voltages, estimate a plurality of read voltages for MLC reading of the plurality of memory cells as estimation values by inputting the histogram into a read voltage estimation model, determine, through MLC reading of the plurality of memory cells using a plurality of sets of read voltages, a set of read voltages for MLC reading as observation values, and update one or more parameters of the read voltage estimation model based on the estimation values and the observation values.

Memory system

According to one embodiment, in a memory system, a memory controller is configured to execute a first operation of observing an optimum value of a read voltage and updating a set value based on the observation result of the optimum value, at a predetermined time point of a plurality of time points for updating the set value of the read voltage for a plurality of memory cells, and execute a second operation of updating the set value based on the set value updated at one previous time point without executing the observation of the optimum value, at a time point after one time point of the predetermined time point.

According to an embodiment, a memory system includes a plurality of memory cells and a memory controller. The memory controller executes a read operation on the plurality of memory cells using one or more reference read voltages to acquire a histogram representing the number of memory cells with respect to a threshold voltage. The memory controller inputs the histogram to a trained neural network model including an output layer for outputting one or more actual read voltages to read data from the memory cells. The memory controller executes a read operation on the memory cells using the one or more actual read voltages output from the output layer.

Memory system and method

A memory controller performs a reference read on a plurality of memory cells using reference read voltages, generates a histogram indicating the number of memory cells in different threshold voltage bins based on results of the reference read, estimates actual read voltages based on the histogram and a first estimation function, and reads data using the actual read voltages. When reading of the data with the actual read voltages estimated using the first estimation function fails, the memory controller estimates actual read voltages using a second estimation function different from the first estimation function and reads the data with the actual read voltages estimated using the second estimation function.

A memory system includes a nonvolatile memory and a memory controller. The memory controller determines a read voltage for first data encoded by a first encoding scheme, by generating a first histogram indicating the number of memory cells for each threshold voltage, and estimating the read voltage using: (a) the first histogram that is corrected based on a first parameter of the first encoding scheme, and a second parameter of a second encoding scheme, and an estimation function for estimating a read voltage for second data encoded by the second encoding scheme, or (b) the uncorrected first histogram, and the estimation function that is corrected based on the first and second parameters, or (c) the first histogram after partial correction based on the first and second parameters, and the estimation function after partial correction based on the first and second parameters.

Memory system configured to estimate a read voltage using a histogram

A display apparatus includes a plurality of surfaces, and a display device provided on at least one surface among the plurality of surfaces. A plurality of communication sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces and configured to perform communication within a predetermined distance, each of the plurality of communication sections including different identification information. A control section is configured to perform control of the plurality of communication sections and the display device. When another display apparatus is connected to the display apparatus, the control section periodically performs time synchronization to synchronize an image displayed on the display device with an image displayed on a display device provided in the other display apparatus.

Display apparatus and display system

There is disclosed a notification method in a communication system of notifying specific multifunctionality information between terminal stations. An expansion code is generated from both a user input code and a function identification code corresponding to a specific function. A transmission frame including the expansion code is also generated and transmitted to at least one of the terminal stations.

Method of notifying function identification information and communication system

A wireless communication apparatus includes a plurality of antennas, and a controller configured to cause a multicast frame including distribution data and a return request to be transmitted from the antennas, and the multicast frame to be re-transmitted when the antennas receive one or more return frames as a response to the multicast frame and an intensity of the return frames meets a predetermined condition.

Wireless communication apparatus, wireless communication system, and wireless communication method

According to an embodiment, a display block is a display apparatus including a plurality of surfaces. The display block includes a display device, a plurality of transmitting/receiving sections that perform communication within a predetermined distance, and a control section. The display device is provided on at least one surface of the plurality of surfaces. The plurality of transmitting/receiving sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces. The control section performs control of the plurality of transmitting/receiving sections and the display device.

According to one embodiment, a transmission system includes a transmitter and a receiver. The transmitter includes a modulator configured to modulate transmission data at a chip rate to generate a modulation signal, and one or a plurality of light sources configured to emit visible light according to the modulation signal. The receiver includes a light receiver having one or more lines of light receiving elements to receive light in a first range including the visible light; and a demodulator configured to demodulate image data generated according to the light received by the light receiver to generate reception data corresponding to the transmission data. A following equation is satisfied ff&#x3c;fm where fm is the chip rate, and ff is a frame rate of the light receiver.

Transmission system, transmitter and receiver

According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s&#x3c;t) symbols on read data, and a second error correction decoding units that perform an error correction decoding process of correcting t symbols on read data from which an error is detected after the error correction decoding process of correcting s symbols.

Memory controller, semiconductor storage device, and decoding method

According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

Storage device

When a wireless communication apparatus transmits a data frame requesting an ACK frame, it is expected that a receiver station will transmit the ACK frame. A preamble analyzer analyzes whether or not a preamble pattern added to the header of a received frame exists from the time it is expected that the ACK frame will be received. When a desired preamble pattern is detected, the preamble analyzer supplies instructions to start an operation of demodulating a reception signal to a demodulator via a controller.

Growing community of inventors

Yokohama, Japan

Koji Horisaki