Hitachi, Ltd.

Hitachi Video Engineering, Incorporated

Koji Fukuda

Hiroki Yamashita

Yasuyuki Kudo

Hideki Endo

Kenichi Sakamoto

Masayuki Takase

Masayoshi Yagyu

Hidehiro Toyoda

Shotaro Tamayama

Noboru Katohno

Chiaki Hirai

Mariko Miyaki

Fumio Yuuki

Yukiko Morimoto

Kazuhiro Ikegaya

Daisuke Hamano

Fumio Yuki

Display screen with graphical user interface

A simulation system obtains multiple random number vectors and a parameter vector and calculates realized values of the behavior of a stochastic system corresponding to each obtained random number vector. Based on each obtained random number vector, on the obtained parameter vector, and on a weight function, the system calculates the weight of each obtained random number vector regarding each of the parameters in the obtained parameter vector, and calculates an evaluation value of the behavior of the stochastic system corresponding to each obtained random number vector. Based on the calculated behavior evaluation value corresponding to each obtained random number vector and on the weight of each obtained random number vector regarding the parameter selected from the obtained parameter vector, the system calculates the sensitivity of an expected value for the behavior evaluation value of the stochastic system with regard to the selected parameter.

Simulation system and simulation method

A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND(MNDand MND) and MND(MNDand MND) are connected to drain outputs of NMOS transistors MNand MNoperated according to differential input signals Din_p and Din_n, respectively. The MNDis arranged adjacent to the MN, and a source of the MNDa and a drain of the MNshare a diffusion layer. The MNDis arranged adjacent to the MN, and a source of the MNDand a drain of the MNshare a diffusion layer. The MNDand the MNDfunction as dummy transistors for suppressing variations in process of the MNand the MNand, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MNor the MN

Semiconductor integrated circuit device

The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C_GOOD and C_BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C_GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted. Depending on a relation among data outputs of total three symbols obtained by combining a symbol and symbols previous and subsequent thereto, it is selected that either the Early or the Late is to be outputted by a decision logic EL_LOGIC.

Data judgment/phase comparison circuit

Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN, PGENfor generating a pulse signal upon a transition of data input signals DIN_P, DIN_N, and current-signal generation circuit blocks ISG_BKp, ISG_BKn, for driving TXP, TXN by current for the duration of a pulse width of the pulse-signal. The current-signal generation circuit block executes high-speed charging of parasitic capacitors Cp, Cp, occurring to TXP, TXN, respectively, while executing charging of parasitic capacitors Cp, Cp, occurring to impedance Zrespectively. VSG_BK decides a voltage level at TXP, TXN, in the stationary state, keeping TXP, TXN as terminal nodes at impedance Z, respectively.

Output driver circuit

A high-accuracy phase detector circuit compatible with a 1/N rate architecture is provided. The phase detector circuit has as many as N track-and-hold circuits for tracking and holding N-phase clock signals CLKto CLK_N in synchronization with a rising edge of input data signal DIN. Out of the N-phase clock signals CLKto CLK_N outputted from as many track-and-hold circuits, only the one whose rising edge is most synchronized with a rising edge of the input data signal DIN is selected and outputted as a phase difference signal.

Phase detector circuit for clock and data recovery circuit and optical communication device having the same

A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.

Signal recovery circuit

A clock data recovery circuit that supplies stable reference clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2&#x3c0;. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reference clock.

Clock data recovery circuit

There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC, PWCLC, for generating a pulse-width adjust-level VCNT on the basis of preceding input data units Din_P, Din_N, respectively, pulse-width adjustment circuits PWCC, PWCC, for adjusting a pulse-width according to VCNT, respectively, and a waveform shaping circuit WAC for shaping a waveform of an output signal from each of the pulse-width adjustment circuits. The pulse-width adjustment circuit has a driving power to be controlled according to a consecutive bits count of each of the preceding input data units, and varies transition time of each of output data units Do_P, Do_N, thereby adjusting the pulse width. With the use of such a waveform equalization scheme as above, it is possible to attain reduction in power consumption due to simplification in circuit configuration, and further, use of CMOS circuits will enable power consumption to be held back to a low level.

Waveform equalization circuit with pulse width modulation

A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting. In addition, the sampling and holding circuit with resetting receives a burst transmission end signal and resets the held value to an initial value.

Clock recovery circuit

In pulse width control equalization, attention is paid to the existence of the symmetry of anteroposterior signals and thereby the size of a table in which the adjustment amount of an edge position is stored is reduced to the power of one-half. Pattern jitters caused by inter-symbol interference are suppressed. The pulse time span of each symbol is adjusted to an optimum pulse width determined by a calculating formula or search in a table in response to a code sequence to be transmitted. In the configuration wherein a table is used, the table to store an edge position adjustment amount wherein the row of the exclusive OR of two symbols located at positions symmetrical to each other before and after a center symbol now ready to be sent in the code sequence is used as a search key is made.

Pulse amplitude modulation circuit with pulse width equalization

The present invention is to provide a semiconductor integrated circuit device provided with a sufficient margin to variations of input waveforms. For example, the semiconductor integrated circuit device is provided with a clock and data determination circuit receiving an input data signal and a clock signal and outputting a recovered data signal, a first phase comparison signal and a second phase comparison signal and a clock signal generating circuit generating the clock signal with a phase corrected based on the first phase comparison signal and the second phase comparison signal. The clock and data determination circuit latches the input data signal in synchronization with the clock signal using a plurality of thresholds as determination reference and generates two kinds of candidates composed of combination of a recovered data signal and phase comparison signals by processing a latch result. Further, one of the two kinds of candidates is selected by a selector circuit based on a symbol of a recovered data signal at a previous cycle.

For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an 'H' level and a latch part that latches a data output signal from the data acquisition part when the click signal is an 'L' level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an &#x201c;L&#x201d; level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.

Logic circuit

In a tape loading mechanism for recording and/or playback equipment in which a magnetic tape is drawn from a cassette to be wound around a cylinder having a head at a predetermined angle, an elongated member for moving drawing members to draw the magnetic tape from the cassette is disposed and extends in a space between a rotating shaft of a cylinder motor for rotating the cylinder identical with a rotational shaft of the cylinder motor and a capstan motor for rotating a capstan shaft identical with the capstan shaft which feeds the magnetic tape together with a pinch roller.

Growing community of inventors

Fuchu, Japan

Koji Fukuda