Socionext Inc.

Fujitsu Corporation

Fujitsu Semiconductor Limited

Koji Banno

Tomoyuki Yamada

Tomoharu Awaya

Takayoshi Minami

Shigetoshi Takeda

Fumio Ushida

Kenji Suzuki

Toru Osajima

Hiroyuki Yamamoto

Takashi Yoneda

Takanori Nawa

Masuo Inui

Koji Tsuneto

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Semiconductor device and method of producing semiconductor device

Semiconductor device, moisture-resistant frame, groove and method of producing semiconductor device

A method of determining wire layouts of a circuit in a semiconductor device that includes a plurality of modules each corresponding to a circuit block includes the steps of providing module terminals of modules to be connected together in a same single layer, determining layouts of wires connected to the module terminals inside the respective modules by laying out the wires in one or more layers no higher than the single layer, and determining layouts of inter-module wires connecting between the module terminals by laying out the inter-module wires in the one or more layers no higher than the single layer.

Method and system for designing wire layout without causing antenna error

In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.

Method of designing wiring for power sources in a semiconductor chip, and a computer product

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Kawasaki, Japan

Koji Banno