Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Panasonic Corporation

Other

Symetrix Corporation

Kojundo Chemical Laboratory Co., Ltd.

Koji Arita

Yasuhiro Shimada

Yoshihisa Nagano

Atsuo Inoue

Akihiro Matsuda

Toru Nasu

Carlos Alberto Paz De Araujo

Yasuhiro Uemoto

Takumi Mikawa

Eiji Fujii

Tatsuo Otsuki

Masamichi Azuma

Larry D McMillan

Shinichiro Hayashi

Yuji Yoshida

Taketoshi Matsuura

Takeshi Tomizawa

Yoshio Kawashima

Nobuyuki Yoshiike

Takeki Ninomiya

Masami Funakura

Kiyoshi Uchiyama

Yasufumi Izutsu

Takeshi Takagi

Takashi Okada

Joseph D Cuchiaro

Mitsuteru Iijima

Satoru Fujii

Susumu Kobayashi

Narayan Solayappan

Yukio Hayakawa

Kazuo Nakatani

Gota Kano

Katsuya Morinaka

Kenji Tominaga

Mitsuhiro Ikoma

Michael C Scott

Satoru Mitani

Ryoko Miyanaga

Jolanta Bozena Celinska

Vikram Joshi

Hidekimi Kadokura

Mariko Kawaguri

Atsushi Himeno

Minoru Tagashira

Masamichi Matsumoto

Eigi Fujii

Katuya Morinaka

Hiroichi Goto

Yukoh Hochido, Deceased

Mikawa Takumi

A current steering element () formed such that the current steering element covers a lower opening () of a via hole () formed in an interlayer insulating layer (), comprises: a corrosion-suppressing layer () formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer () formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer () formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer () formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.

Current steering element and non-volatile memory element incorporating current steering element

Disclosed is a memory device provided with a plurality of memory cells and a lead-out line () shared among the memory cells. Each memory cell is provided with a transistor () formed above a substrate () and a variable resistance element () having a lower electrode (), an upper electrode () that comprises a noble metal, and a variable resistance layer () disposed between the lower electrode () and the upper electrode (). The resistance value of the variable resistance layer () changes reversibly in response to electric pulses that go through the transistor () and are applied between the lower electrode () and the upper electrode (). The lead-out line () is in direct contact with the upper electrodes () of the memory cells.

Memory device and method of manufacturing the same

A nonvolatile semiconductor memory device () comprises a substrate () provided with a transistor (); a first interlayer insulating layer () formed over the substrate to cover the transistor; a first contact plug () formed in the first interlayer insulating layer and electrically connected to either of a drain electrode () or a source electrode () of the transistor, and a second contact plug () formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer () formed to cover a portion of the first contact plug; a first wire () formed on the resistance variable layer; and a second wire () formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.

Nonvolatile semiconductor memory device having coplanar surfaces at resistance variable layer and wiring layer and manufacturing method thereof

Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode (), a second electrode (), and a current steering layer (). The current steering layer () comprises SiN(where 0&#x3c;x&#x2266;0.85) added with hydrogen or fluorine. When D (D=D&#xd7;10atoms/cm) represents a density of hydrogen or fluorine, d (nm) represents a thickness of the current steering layer (), and V(V) represents a maximum value applicable to between the first electrode () and the second electrode (), D, x, d, and Vsatisfy the following Formulae.(ln(10000(&#xb7;exp(&#x3b1;&#xb7;)exp(&#x3b2;&#xb7;)))&#x3b3;)(ln(1000(&#xb7;exp(&#x3b1;&#xb7;)exp(&#x3b2;&#xb7;)))&#x3b3;)&#x2212;(ln(10000(&#xb7;exp(&#x3b1;&#xb7;)exp(&#x3b2;&#xb7;)))&#x3b3;)/2&#x2267;0

Current steering element, memory element, memory, and method of manufacturing current steering element

A nonvolatile memory element comprises a first electrode (); a second electrode (); and a resistance variable layer () disposed between the first electrode () and the second electrode (), resistance values of the resistance variable layer reversibly changing in response to electric signals applied between the electrodes (); the resistance variable layer () including a first tantalum oxide layer () comprising a first tantalum oxide and a second tantalum oxide layer () comprising a second tantalum oxide which is different in oxygen content from the first tantalum oxide, the first tantalum oxide layer and the second tantalum oxide layer being stacked together, and being configured such that 0&#x3c;x&#x3c;2.5 is satisfied when the first tantalum oxide is expressed as TaOand x&#x3c;y&#x2266;2.5 is satisfied when the second tantalum oxide is expressed as TaO; and the second electrode () being in contact with the second tantalum oxide layer () and comprising platinum and tantalum.

Nonvolatile memory element, nonvolatile memory device, nonvolatile semiconductor device, and method of manufacturing nonvolatile memory element

A nonvolatile memory element includes a first electrode () formed on a substrate (), a resistance variable layer () and a second electrode (), wherein the resistance variable layer has a multi-layer structure including at least three layers which are a first transition metal oxide layer (), a second transition metal oxide layer () which is higher in oxygen concentration than the first transition metal oxide layer (), and a transition metal oxynitride layer (). The second transition metal oxide layer () is in contact with either one of the first electrode () and the second electrode (). The transition metal oxynitride layer () is provided between the first transition metal oxide layer () and the second transition metal oxide layer ().

Nonvolatile memory element and nonvolatile memory device incorporating nonvolatile memory element

A memory element () arranged in matrix in a memory device and including a resistance variable element () which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element () for controlling a current flowing when the electrical pulse is applied to the resistance variable element (); wherein the current control element () includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiN, and at least one of the first electrode and the second electrode comprises &#x3b1;-tungsten.

Current control element, memory element, and fabrication method thereof

A resistance variable element () used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate () and an interlayer insulating layer () formed on the substrate, and have a configuration in which a through-hole () is formed to penetrate the interlayer insulating layer, a first resistance variable layer () comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer () comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening () of the through-hole which is closer to the substrate.

Resistance variable element and resistance variable memory device

A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element () including: a variable resistance element () whose electric resistance value changes in response to application of electric pulses having a positive polarity and a negative polarity and which maintains the changed electric resistance value; and the current steering element () that steers current flowing through the variable resistance element () when the electric pulses are applied, the current steering element () includes: a first electrode (); a second electrode (); and a current steering layer () interposed between the first electrode () and the second electrode (). When the current steering layer () includes SiN(0&#x3c;x&#x2266;0.85) and a thickness of d [nm], a relationship between a nitrogen composition ratio x and the thickness d is in a range represented by a predetermined conditional expression.

Current steering element, storage element, storage device, and method for manufacturing current steering element

A method of manufacturing a memory cell array in which first conductive layers () and second conductive layers () extend above a semiconductor substrate () and three-dimensionally cross with each other, and memory cells each of which includes a current steering element () and a variable resistance element () electrically connected in series to each other is provided at a corresponding one of three-dimensional cross points between the first conductive layers () and the second conductive layers (). The method includes: forming a first interlayer insulating film (); forming a contact hole in the interlayer insulating film (); depositing a first plug material () in the contact hole and on the first interlayer insulating film (); performing a first polishing in which the first plug material () is polished until the first interlayer insulating film () is exposed; depositing a conductive film () that becomes a first electrode () of the current steering element (), on the first plug material () and the first interlayer insulating film () after the first polishing; and performing a second polishing in which a surface of the conductive film () is polished.

Memory cell array, nonvolatile storage device, memory cell, and method of manufacturing memory cell array

In a current rectifying element (), a barrier height &#x3c6;A of a center region () of a barrier layer () in a thickness direction thereof sandwiched between a first electrode layer () and a second electrode layer () is formed to be larger than a barrier height &#x3c6;B of a region in the vicinity of an interface () between the barrier layer () and the first electrode layer () and an interface () between the barrier layer () and the second electrode layer (). The barrier layer () has, for example, a triple-layer structure of barrier layers (), () and (). The barrier layers (), () and () are, for example, formed by SiN layers of SiNx, SiNx, and SiNx(X1&#x3c;X2). Therefore, the barrier layer () has a barrier height in which the shape changes in a stepwise manner and the height of the center regionis large.

Current rectifying element, memory device incorporating current rectifying element, and fabrication method thereof

A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.

Method for manufacturing nonvolatile storage element and method for manufacturing nonvolatile storage device

A lower electrode () is provided on a semiconductor chip substrate (). A lower electrode () is covered with a first interlayer insulating layer () from above. A first contact hole () is provided on the lower electrode () to penetrate through the first interlayer insulating layer (). A low-resistance layer () forming the resistance variable layer () is embedded to fill the first contact hole (). A high-resistance layer () is provided on the first interlayer insulating layer () and the low-resistance layer (). The resistance variable layer () is formed by a multi-layer resistance layer including a single layer of the high-resistance layer () and a single layer of the low-resistance layer (). The low-resistance layer () forming the memory portion () is isolated from at least its adjacent memory portion ().

Nonvolatile memory element array with storing layer formed by resistance variable layers

A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.

Semiconductor memory device

Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400&#xb0; C. and then furnace annealed in oxygen at a temperature of between 600&#xb0; C. and 850&#xb0; C.

Metal oxide integrated circuit on silicon germanium substrate

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Osaka, Japan

Koji Arita