Fuji Xerox Co., Ltd.

Renesas Electronics Corporation

Toyota Jidosha Kabushiki Kaisha

Fuji Xerox Corporation

Koji Adachi

Kaoru Yasukawa

Tetsuichi Satonaga

Koki Uwatoko

Norikazu Yamada

Eigo Nakagawa

Masayasu Takano

Shigehiro Furukawa

Noriyuki Matsuda

Akiko Seta

Hiroshi Ishikawa

Koushi Kawamoto

Yoichi Yuyama

Kazunori Miyamoto

Hitoshi Suzuki

Kiyoshi Horie

Yousuke Nakamura

Takeshi Sumikawa

Toshiro Yamamoto

Toru Okamoto

Hirotaka Motai

Yasuhiro Tawara

Junichi Sato

Masahiro Suzuki

Nobumasa Furuya

Kazuo Maruyama

Yoshinori Wada

Tsuneo Noami

Toshiyuki Matsunaga

Masahiko Koyanagi

Teppei Oomoto

Takashi Nagao

Noriaki Seki

Satoshi Kubota

Kenji Ogi

Tetsuro Kawata

Kazuya Okamoto

Kazutaka Hirata

Yasuhiro Sugita

Yuji Onozawa

Tetsuaki Wakabayashi

Tsuneo Naomi

Kazuo Marugama

Furuya Nobumasa

Hidekazu Bingo

Tetuichi Satonaga

A semiconductor device includes a common resource commonly used by plural processes executed on a processor, a semaphore controlling the possessory right of the common resource, and a semaphore management unit performing a process of acquiring the possessory right of the common resource to the semaphore in response to a request of a process performed on the processor. When a request to acquire the possessory right of the common resource is received from a first process in the plural processes and the possessory right cannot be obtained, the semaphore management unit switches the process executed on the processor to a second process, repeatedly performs a process of acquiring the possessory right requested by the first process to the semaphore and, when the possessory right requested by the first process is obtained, switches the process on the processor from the second process to the first process.

Semiconductor device including semaphore management

According to one embodiment, a data processing apparatus includes an access controller configured to control access by a CPU to a processor. The access controller selects permission configuration information and an identifier table to be used for the access control using processor selection information output from the CPU, determines as intermediate identifier MID that corresponds to an access request identifier SPID output from the CPU using the selected identifier table, and determines accessibility of the CPU to the processor using the selected permission configuration information and the determined intermediate identifier MID.

Data processing apparatus and access control method

A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while specifying address, identifier, and access type, and a memory protection resource including an associative memory to perform an access control. The memory protection resource includes a plurality of entries, each including a region setting unit, an identifier determination information unit, and an attribute setting unit. When the address specified by the access subject at the access is included in the region set in the region setting unit in the entry, the identifier agrees with at least one of the identifiers specified according to the identifier determination information, and the specified access type agrees with the access type set in the attribute setting unit, the memory protection resource permits the access.

Data processor

A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated.

Multi-thread processor and its interrupt processing method

A multi-thread processor includes a plurality of hardware threads that generates a plurality of mutually independent instruction streams, respectively and a scheduler that schedules the plurality of hardware threads.

Multi-thread processor with rescheduling when threads are nondispatchable

A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Computer system

The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. A thread waste counter is provided for each hardware thread in the first group and counts up each time a nondispatchable state occurs when the hardware thread is specified by the thread scheduling. When the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.

A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.

The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. Moreover, when the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.

A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that continuously outputs a thread selection signal uniformly in a first period of a cycle of the first schedule pattern in accordance with a first schedule pattern or continuously outputs the thread selection signal uniformly in a second period of a cycle of the second schedule pattern in accordance with a second schedule pattern, the thread selection signal designating a hardware thread to be executed in a next execution cycle from among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread from among the plurality of hardware threads, and an execution pipeline that executes an instruction output from the first selector.

Multithread processor with different schedule pattern cycle state for handling interrupt processing

A multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, and a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread. The thread scheduler specifies execution of at least one hardware thread pre-selected among the plurality of hardware threads in a predetermined first execution period, and specifies execution of a variably selected hardware thread in a second execution period other than the first execution period. A time ratio between the predetermined first execution period and the second execution period is set according to processing requests.

Scheduling threads according to real time bit in predetermined time period or in variable time period of requested time ratio

Provided is an estimation apparatus including a storage unit that stores an estimation model for estimating transport failure information pertaining to a transport failure based on information pertaining to a transit time in which each of plural papers with different characteristics passes through a certain transport section in a transport path and information pertaining to a utilization of each of the plural papers for each of plural image processing apparatuses, an acquisition unit that acquires the characteristics of the paper, information pertaining to the transit time of the paper, and information pertaining to the utilization of the paper for the image processing apparatus that is the estimation target, and an estimation unit that estimates the transport failure information using the estimation model based on the acquisition results of the acquisition unit.

Estimation apparatus

A semiconductor device includes an execution unit that executes an arithmetic instruction, and a scheduler including multiple first setting registers each defining a correspondence relationship between hardware threads and partitions, and which generates a thread select signal on the basis of a partition schedule and a thread schedule. The scheduler outputs a thread select signal designating a specific hardware thread, without depending on the thread schedule as the partition indicated by a first occupation control signal, according to a first occupation control signal output when the execution unit executes a first occupation start instruction.

Thread scheduling in a system with multiple virtual machines

Provided is a parameter setting system, including a storage unit that memorizes a history of parameter values in an image forming apparatus in association with a type of paper, an acquiring unit that acquires a trend of parameter values in plural image forming apparatuses of the same type with the image forming apparatus with respect to each type of plural other paper sheets in which the number of types of switched paper and the number of histories are greater than or equal to a threshold value, and a calculating unit that calculates a parameter value to be set with respect to the type of switched paper based on the trend of parameter values acquired with respect to the type of switched paper and each type of the plural other paper sheets, and the history corresponding to each type of the plural other paper sheets.

Controlling an image forming apparatus according to parameters determined based on paper type history

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Kanagawa, Japan

Koji Adachi