Fujitsu Corporation

Fujitsu Microelectronics Limited

Koji Abe

Hitoshi Watanabe

Masahiro Sano

Eiji Kondo

Seiko Oosaki

Seiko Osaki

A frame input unit receives an input of a frame having a placement area for an element to which a predetermined signal is supplied. A netlist input unit receives an input of a netlist concerning the element. A placing unit places the element in the placement area of the frame input by the frame input unit based on the netlist input by the netlist input unit. A detecting unit detects whether there is a vacant position in the placement area in which the element is placed by the placing unit, and a bypass-element placing unit places a bypass element at the vacant position detected by the detecting unit, the bypass element propagating the predetermined signal by bypassing the element located adjacent to the vacant position.

Layout design apparatus, layout design method, and computer product

An apparatus for designing a layout includes an arranging unit that arranges, on a large-scale-integrated chip, a cell in which a signal line segment that is not connected to a terminal is formed; a wiring unit that wires a signal line to an arbitrary wiring layer of the large-scale-integrated chip; and a connecting unit that connects the signal line segment with the signal line.

Method and apparatus for designing a layout, and computer product

A layout designing apparatus includes an input unit that receives an input of a frame having a boundary scan register, a placing unit that places an I/O macro to be connected to a signal terminal for propagating other signal than a test signal in an arbitrary I/O macro placement area of the frame input, a determining unit that determines whether a frame terminal at an arbitrary terminal position in the frame matches with at least one of a test terminal for propagating the test signal in the frame input and a signal terminal to be connected to the I/O macro placed, and a replacing unit that replaces, based on a result of determining by the determining unit, the I/O macro placed with either of a shared I/O macro and a test-only I/O macro.

Method and apparatus for designing layout, and computer product

In a method of designing a layout of an LSI chip, which LSI chip has boundary scan registers, after arranging I/O cells and before arranging an internal logic circuit and the like, I/O connection boundary scan registers are preferentially arranged in empty regions of the I/O cells. Output I/O control boundary scan registers are arranged at intermediate points between the I/O connection boundary scan registers, respectively, or a chip side closer to the intermediate points. Thereafter, before arranging cells constituting other circuits and creating a wiring pattern, buffer cells are inserted into nets of test signals to the boundary scan register led to a test control circuit.

Method of designing a layout of an LSI chip, and a computer product

A LSI layout designing apparatus which is implemented by a computer and designs a layout of a LSI on a display screen includes a timing adjusting unit for carrying out a timing adjustment process with respect to logic circuit data of the LSI already subjected to a layout process, and a layout restoration unit for restoring an original layout of the LSI prior to the timing adjustment process and reflecting a change of cells caused by the timing adjustment process on the original layout which is displayed on the display screen.

Growing community of inventors

Kawasaki, Japan

Koji Abe