Fujitsu Corporation

Fijutsu Limited

Koichiro Takayama

Tsuneo Nakata

Jawahar Jain

Ryosuke Oishi

Akio Matsuda

Indradeep Ghosh

Rajarshi Mukherjee

Hidetoshi Matsuoka

Koji Hosoe

Akio Tokoyoda

Fumiyasu Hirose

Masatoshi Aihara

Liang Zhang

Shintaro Shimogori

Tomohiro Inoue

Yuichiro Ajima

Shinya Hiramoto

Sreeranga P Rajan

Praveen Murthy

Hiroaki Iwashita

Farzan Fallah

Shun Ando

Masahiro Maeda

Debashis Sahoo

Makoto Suga

Qiang Zhu

Rafael Kazumiti Morizawa

Christian Stangier

Thomas W Sidle

Kioto Hirahara

The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.

Arithmetic processing device storing diagnostic results in parallel with diagnosing, information processing apparatus and control method of arithmetic processing device

An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.

Information processing apparatus, information processing system, and communication device

An information processing apparatus includes: a memory device configured to store data; an arithmetic processor configured to issue a request to be transmitted to the memory device; and a memory controller including: a buffer configured to store one or more unselected requests that are issued by the arithmetic processing processor and are not selected; a history register configured to hold one or more addresses for one or more transmitted requests that have been transmitted to the memory device; and a selection unit configured to select, from the one or more unselected requests stored in the buffer, a target request to be transmitted to the memory device based on the one or more addresses stored in the history register and transmit the target request to the memory device.

Information processing apparatus, memory controller, and memory control method

A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.

Verification supporting system

Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output.

Verification of requirements specification, design specification, and computer-readable storage medium apparatus, and method thereof

In a verification support apparatus, an implementation description of a verification target is acquired and based on the implementation description, a combination of input gates is identified. A pair of output cones including gates to which input signals from the input gates reach, and a common output cone including gates common to the pair of output cones, are detected. Based on the common output cone, a degree of relation between the input gates is calculated and according to the calculation, the strength of relation is determined for the combination of input gates. The strength of relation for a combination of the input gates is set, the combination being based on a specification of the verification target and corresponding to the combination identified from the implementation description. Whether the strength of relation set and that determined for the identified combination coincide is judged and a result of the judgment is output.

Verification support apparatus, verification support method, and computer product

In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.

Verification supporting apparatus, verification supporting method, and computer product

A method and apparatus for generating processor test programs using a formal description of the processor's instruction set. An instruction set for a processor is formally described using a language such as ISDL. The formal description of the instruction set identifies certain characteristics of the instructions making up the instruction set. The formal description is combined with a test specification that describes desired properties of a test program by formally specifying test sequences that are to be applied to instructions having particular characteristics. A test program is generated by applying the formal test specification to the formal description of the instruction set including test sequences applicable to instructions having the particular characteristics.

Method and apparatus for test program generation based on an instruction set description of a processor

In one embodiment, a method for invariant checking includes executing one or more first steps of a finite state machine (FSM) corresponding to one or more binary decision diagrams (BDDs) to traverse a state space of the FSM in a first direction with respect to an initial state and an erroneous state. The method also includes, automatically and without user input, accessing a first profile corresponding to the one or more first steps of the FSM, comparing the first profile with one or more first predetermined criteria, stopping the traversal of the state space in the first direction according to the comparison between the first profile and the one or more first predetermined criteria, executing one or more second steps of the FSM to traverse the state space in a second direction with respect to the initial state and the erroneous state opposite the first direction according to a first partial result from the one or more first steps of the FSM, accessing a second profile corresponding to the one or more second steps of the FSM, comparing the second profile with one or more second predetermined criteria, stopping the traversal of the state space in the second direction according to the comparison between the second profile and the one or more second predetermined criteria, and executing one or more third steps of the FSM to traverse the state space in the first direction from the one or more first steps according to a second partial result from the one or more second steps of the FSM.

Invariant checking

In one embodiment, a method for circuit verification using multiple engines includes running multiple traces on a circuit using multiple reachability algorithms, selecting an effective reachability algorithm for the circuit from among the multiple reachability algorithms according to a comparison of results of the multiple traces with each other, generating a set of initial states for the selected effective reachability algorithm using states reached in the plurality of traces, and executing the selected effective reachability algorithm using the generated set of initial states to verify the circuit.

Circuit verification using multiple engines

A method for high level validation of a design includes receiving input associated with a design; generating a message diagram in response to the input, wherein the message diagram describes a relationship of messages communicated between multiple processes; resolving at least one scenario from the message diagram, wherein the scenario comprises a particular sequence of messages identified by the message diagram; generating a state machine operable to receive and transmit at least some of the messages identified by the message diagram according to the scenario; and testing an implementation of the design using the state machine.

High level validation of designs and products

Propagating an error through a network includes receiving a network having propagation paths and nodes, where a propagation path has one or more nodes and a node is associated with a variable operable to have a value during simulation. A tag of a tag set is assigned to the value. The tag set includes at least two signed tags, positive tag representing a positive error and a negative tag representing a negative error, and an unsigned tag representing an error having an unknown sign. The tag is propagated along the propagation path to yield intermediate tags, where at least one intermediate tag is an unsigned tag formed from at least two signed tags. A final tag is determined in accordance with the intermediate tags in order to propagate an error through the network.

Propagating an error through a network

Evaluating a validation vector includes receiving a network having nodes and a target set that includes one or more nodes of the network. The following steps are repeated until the nodes of the target set have been selected. A node is selected from the target set, and a tag is assigned to the node, where the tag represents an error of a value of a variable corresponding to the node. A test environment specifying a propagation path from an input, through the node, and to an output is generated. The test environment is translated into a validation vector, and the tag is propagated to the output according to the validation vector. After repeating the steps, coverage for the validation vectors is determined in accordance with the propagation to evaluate the one or more validation vectors.

Evaluating a validation vector for validating a network design

All nodes in a network are classified into hierarchical groups. Each node belongs to any group in all hierarchical groups from the highest order group to the lowest order group. The node is assigned a hierarchical address corresponding to each hierarchical group. Thus, the amount of routing information required for data transfer can be reduced, thereby efficiently transmitting data.

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Kawasaki, Japan

Koichiro Takayama