Hitachi, Ltd.

Koichiro Omoda

Shigeo Nagashima

Shunichi Torii

Teruo Tanaka

Yasuhiro Inagami

Takayuki Nakagawa

Naoki Hamanaka

Junji Nakagoshi

Yoshiharu Kazama

Shunsuke Miyamoto

Yoshiaki Kinoshita

Mitsuru Nagasaka

Kazuo Ojima

Mamoru Sugie

Yoshio Takamine

Hozumi Hamada

Masayuki Miyoshi

Sakae Takahashi

A parallel processor system which includes a plurality of processors each for executing at least one of a plurality of mutually associated programs and a transfer circuit. The transfer circuit is connected to the processors, and is provided for transferring the data outputted from any one of the programs during execution of one program by any one of the processors to other processors to which a receiving program is allotted. The transfer operation is performed in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.

Data transfer method of transferring data between programs of a same

A parallel processor system includes a transfer circuit and a plurality of processors each of which executes at least one of a plurality of mutually associated programs. The transfer circuit transfers data from a sending program allotted to one processor to a receiving program allotted to another processor by identifying the other processor and the receiving program based on a job number and within-job process number outputted by the sending program.

System for converting job/process identifiers into processor/process

A plurality of data banks operable independently from each other is controlled by a control circuit so that a set of received data signals are written into respective storage locations predetermined for respective data signals within respective data banks predetermined for respective data signals, wherein respective storage locations and respective data banks for respective received data signals are predetermined depending upon the arrival numbers of respective received data signals and a predetermined bank order, so that respective storage locations for two data signals received one after another belong to different data banks arranged according to the bank order. The data banks are controlled by the control circuit so that a set of data signals are read out according to the order of receipt of the set of data signals and from a timing before completion of the writing of the set under a condition that each data bank performs only one of write and read operations during a clock period.

Data storage device

In a multiprocessor digital computer system ID data, coupled with data for which inter-processor communication is desired, is communicated from one processor and held temporarily with data in a receiver buffer (associative memory) in a receiving processor. This ID is divided into main ID data MK and sub ID data SK. Main ID data MK is used for searching data from a receive buffer. The sub ID data SK are used as an ID of the data in the receive processor.

Parallel computer with asynchronous communication facility

A parallel processor system having a plurality of processor elements includes transfer information generation circuit for generating transfer information by adding to vector data a data identifier for the vector data and a destination processor element number, transmission circuit for sending the transfer information to a data communication path, receive circuit for holding the transfer information sent from the data communication path, and vector register for continuously reading related element data from the receive circuit based on the data identifiers generated by the transfer information generation circuit.

Method and apparatus for transferring vector data between parallel

A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected to the writing circuit and to the reading circuit, and which ensures the sequence of main storage references between said writing circuit and said reading circuit such that said reading circuit will not read the data elements that have not yet been written by said writing circuit among said group of data elements.

Computer for synchronized read and write of vector data

In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided. The vector buffer storage control checks if the identification information of the vector data designated by a vector data fetch instruction for the main storage is in the indentification storage, and if it is in the identification storage, it fetches the vector data from the buffer storage and transfers it to the vector register, and if it is not in the identification storage, it instructs to fetch the vector data from the main storage, transfers the vector data fetched from the main storage to the vector register and stores it into the buffer storage.

Vector processor with vector buffer memory for read or write of vector

A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.

Circuit simulation method with clock event suppression for debugging LSI

A vector processor having a vector register made up of elements of l.sub.2 -byte size for storing vector data made up of a plurality of elements read out from a main storage which has a plurality of storage areas and is capable of reading out data of l.sub.1 -byte size beginning from a specified address bound, and adapted to write vector data with an element size of m (l.sub.1 /m is an integer and l.sub.2 is larger or equal to m) into the vector register sequentially, read-out vector data from the vector register for computation by an arithmetic unit, and write the computational result into the vector register, wherein the processor writes elements of vector data read out from the main storage into separatte, specified locations of the vector register in an order required for subsequent operations.

Vector processor for reordering vector data during transfer from main

A vector logical operation apparatus includes first and second registers respectively for sequentially receiving first and second sets of vector elements which first and second sets of vector elements are supplied in pairs on the same sequential clock periods; third register; a plurality of first gates connected to the first and third registers each for performing a first bitwise logical operation on bit signals partly provided from the first register and the third register; a plurality of second gates connected to the second register and the first gates in a bitwise manner each for performing a second bitwise logical operation on bit signals provided from the second register and the first gates; a feed back circuit connected to the plurality of second gates for supplying the outputs of the second gates to the third register; and control circuit connected to the third register for ordering the third register to receive an applied initial data signal on or before supply of a pair of the first vector element of the first set and second set and to repeatedly receive the outputs of the second gates provided by the feed back circuit on sequential clock periods each clock period being one clock period later after receipt a pair of vector elements by the first and second registers; wherein the first and second gates are operable fast enough so that the outputs of the second gates at the end of each clock period fully responds to vector elements held by the first to third registers at the beginning of each clock period.

Selectively recursive pipelined parallel vector logical operation system

In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.

Vector processor capable of parallely executing instructions and

In a vector processor for performing an operation on first and second vectors for each vector element, an operation code is set for each vector element of at least one of the first and second vectors to designate the type of an operation to be executed on the vector element, and the operation is carried out on the first and second vectors for each vector element based on the operation code.

Vector operation designator

A unit operative in concurrence with a vector processing for beforehand sequentially generating page addresses containing vector data to be referred to thereafter and a unit for achieving a processing to determine whether or not a page fault occurs in a page in an address translation and responsive to an occurrence of a page fault in a page for executing processing to beforehand transfer the page to a main storage are provided. Even if a vector element existing in the page becomes necessary in the vector processing after the operation described above, another paging processing is not necessary because the page exists in the main storage.

Vector data refer circuit with a preceding paging control for a vector

A data processor for latching in a floating point register floating point data having exponent parts of fixed and variable lengths, which are transferred from a main storage or an arithmetic unit as they are, but are not converted to another data expression type. When the data of the two representation types are to be input for computations from the floating point register or storage to the arithmetic unit, there is provided circuitry for controlling the data to be computed after that data has been converted into data having an exponent part of fixed length representation, in the arithmetic case of data having an exponent part of the variable length representation, and data to be computed without any data conversion in the arithmetic case of data having an exponent part of the fixed length representation. By thus controlling the two computations discriminatively, it is possible to realize the processing time periods matching the respective data widths.

Data processor capable of processing floating point data with exponent

A data processing system having a plurality of FIFO memories and a plurality of ALUs and in which a FIFO memory may be selected to receive a set of data signals from an ALU and at the same time to be selected to provide a set of data signals to another ALU, with the result that the selected FIFO memory performs read and write operations concurrently and intermittently. Also, a set of data signals held by one of the FIFO memories may be transferred to a selected ALU for effecting a logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation by the selected ALU may be transferred to another FIFO memory.

Growing community of inventors

Sagamihara, Japan

Koichiro Omoda