Mitsubishi Denki Kabushiki Kaisha

Semiconductor Technology Academic Research Center

Koichiro Mashiko

Kiyohiro Furutani

Kazutami Arimoto

Noriaki Matsumoto

Yoshio Matsuda

Kimio Ueda

Hiroyuki Morinaka

Haruo Kobayashi

Yoshiki Wada

Hiroaki Suzuki

Toshifumi Kobayashi

Shoji Kawahito

Hiroshi Miyamoto

Kuniyuki Tani

Yoshikazu Morooka

Michihiro Yamada

Yasuhide Shimizu

Koji Sushihara

Akira Kurauchi

Kazuya Shimizu

Yoshiki Niki

Tetsuro Itakura

Hiroshi Makino

Tadato Yamagata

Hirotada Kuriyama

Tatsuji Matsuura

Akira Abe

Yosuke Sakai

Yuto Ikeda

Takanori Hirota

Shigetaka Takagi

Toshio Ichiyama

Makoto Taniguchi

Masato Kaneta

Kazutaka Honda

Katsuyoshi Yagi

Zheng Liu

Masafumi Uemori

Tomonari Ichikawa

A signal processing method and apparatus reducing distortion using divided signals differing in only amplitude by weighting an input signal by first weights k(i=1 to 4) to obtain divided signals, performing the same signal processing f(x) on the divided signals, weighting the signal processed divided signals by second weights l(i=1 to 4), and adding the divided signals Vto Vweighted by the second weights. The first weights are k=t, k=&#x2212;t, k=1, k=&#x2212;1, while the second weights are l=t, l=&#x2212;t. Here, t=b/a (whereandare different positive integers).

Signal processing method and signal processing apparatus

A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

Differential operational amplifier circuit correcting settling error for use in pipelined A/D converter

A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a difference between the first delay amount and the second delay amount is smaller than the first delay amount and the second delay amount.

Time-to-digital converter

A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

Sample hold circuit for use in time-interleaved A/D converter apparatus including paralleled low-speed pipeline A/D converters

An AD converter that operates at high speed and precision of which is disclosed. The AD converter includes an analog-to-digital (AD) conversion part that samples an analog signal according to a sampling clock and converts it into a digital signal, a jitter measuring circuit that measures the jitter of the sampling clock, and a correction circuit that corrects a digital signal output from the AD conversion part. The AD converter further comprises a clock source and a sampling generating circuit that generates a sampling clock by dividing the clock generated by the clock source, wherein the jitter measuring circuit measures the jitter of the sampling clock with respect to the click on the basis of a clock CK.

Analog-to-digital (AD) converter and analog-to-digital conversion method

A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area.

Current mirror circuit

There is disclosed a current mirror circuit comprising a first transistor having a first electrode connected to a first potential, a second electrode connected to a second potential lower than the first potential, and a third electrode connected to a third potential higher than the second potential, a second transistor having a first electrode connected to the first potential and the first electrode of the first transistor, and a second electrode connected to the second potential, an operational amplifier having a high-potential input connected to the third potential and the third electrode of the first transistor, and a low-potential input connected to the third electrode of the second transistor, and a third transistor having a first electrode connected to an output of the operational amplifier, a second electrode connected to the low-potential input and the third electrode of the second transistor, and a third electrode used as an output terminal.

A continuous-time band-pass &#x394;&#x3a3; AD modulator subtracts an analog signal from a DA converter from an inputted analog signal, outputs an analog signal having a subtraction result to an AD converter via a continuous-time analog band-pass filter, outputs a digital signal from the AD converter to the DA converter, and outputs the same digital signal as a digital signal subjected to a band-pass &#x394;&#x3a3; AD modulation processing. The highest input frequency 'fin' of the inputted analog signal is substantially set to three-fourths of a sampling frequency 'fs'. The DA converter is configured to convert the inputted digital signal into the analog signal, and outputs the analog signal, which is inverted or not in response to a value of the inputted digital signal and has an amplitude of substantially zero and a gradient of substantially zero at a timing k/(2fs).

Band-pass &#x394;-&#x3a3; AD modulator for AD-converting high frequency narrow-band signal with higher precision and lower power consumption

A portable information system having an information registration function achieves reduction in manufacturing cost and power consumption. By connecting portable information equipment ( ) and a battery charger ( ) to be chargeable, signal transmission becomes possible between a micro controller ( ) in the portable information equipment ( ) and a micro controller ( ) in the battery charger ( ). Under the control of the micro controllers ( ), information management operation is automatically performed during charging. The operation includes backup processing in which personal information stored in a storage portion ( ) in the portable information equipment ( ) is transferred to a storage portion ( ) in the battery charger ( ) as backup information, and restore processing in which the backup information stored in the storage portion ( ) is transferred to the storage portion ( ) as the personal information.

Portable information equipment system

A Silicon-On-Insulator (SOI) CMOS circuit includes a plurality of PMOS transistors connected in series to each other and at least one NMOS transistor connected to one of the PMOS transistors. The NMOS transistor has its body connected to a low reference potential having a value of ground. The SOI CMOS circuit further includes a body potential generating circuit which generates a body potential between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential. The body potential generating circuit applies the high potential to the bodies of the PMOS transistors.

Silicon-on-insulator CMOS circuit

A portable information system having an information registration function achieves reduction in manufacturing cost and power consumption. By connecting portable information equipment (,) and a battery charger (,) to be chargeable, signal transmission becomes possible between a micro controller (,) in the portable information equipment (,) and a micro controller (,) in the battery charger (,). Under the control of the micro controllers (,), information management operation is automatically performed during charging. The operation includes backup processing in which personal information stored in a storage portion (,) in the portable information equipment (,) is transferred to a storage portion (,) in the battery charger (,) as backup information, and restore processing in which the backup information stored in the storage portion (,) is transferred to the storage portion (,) as the personal information.

A field shield portion consisting of a kind of transistor is formed to electrically insulate an NMOS region of a memory cell from other regions. The field shield portion includes a field shield gate electrode layer, a p type region and a gate insulating film. Threshold value of this transistor is set higher than the power supply voltage, and field gate electrode layer thereof is in a floating state. It is unnecessary to provide a contact portion for applying a prescribed voltage at field shield gate electrode layer. Therefore, the region for forming the contact portion in field shield gate electrode layer can be reduced. As a result, a semiconductor device of which layout area is reduced, is provided.

SOI Semiconductor device with field shield electrode

A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.

Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate

In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption. Further, with positional relation between the body contact regions (9), (10) and the gate contact regions (5), (7), the device is capable of freely setting the transistors to be of either a gate control type or a gate fixed type. As a result, the gate array type semiconductor device achieves high-speed operation and low power consumption.

Gate array semiconductor device

A semiconductor integrated circuit including a first MOS transistor supplied with a first power supply voltage and having a high threshold voltage; a second MOS transistor supplied with a second power supply voltage and having the high threshold voltage; a logic circuit connected between the first transistor and the second transistor and including a plurality of MOS transistors having a low threshold voltage; a control circuit for generating a control signal when the logic circuit is in a standby state; and a voltage generating circuit for generating a first voltage which is a higher than the first power supply voltage and a second voltage which is a lower than the second power supply voltage, for supplying the first voltage to a gate of the first MOS transistor and for supplying the second voltage to a gate of the second MOS transistor when the logic circuit is in the standby state, thereby to decrease leakage current through the first and second transistors and through the logic circuit when in the standby state.

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Hyogo, Japan

Koichiro Mashiko