Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Other

Hitachi Ulsi Engineering Corp.

Matsushita Electric Industrial Co., Ltd.

Hitachi Vlsi Engineering Corp.

Semiconductor Technology Academic Research Center

Hitachi Engineering Co., Ltd.

Renesas Electronics Corportion

Koichiro Ishibashi

Kenichi Osada

Hiroyuki Mizuno

Shuji Ikeda

Masanao Yamaoka

Masayuki Miyazaki

Toshiaki Yamanaka

Naotaka Hashimoto

Katsuro Sasaki

Shigezumi Matsui

Kiyoo Itoh

Masataka Minami

Susumu Narita

Akio Nishida

Nobuyuki Moriwaki

Takanori Shimura

Yoshikazu Saitoh

Naoki Kitai

Masaru Nakamichi

Satoshi Meguro

Hiroshi Makino

Atsuyoshi Koike

Koji Nii

Hirofumi Shinohara

Shigeki Obayashi

Osamu Minato

Hisayuki Higuchi

Toshihiro Hattori

Soichiro Hashiba

Isamu Kuramoto

Yutaka Kobayashi

Kunio Uchiyama

Atsushi Hiraishi

Yasuhisa Shimazaki

Junichi Nishimoto

Goichi Ono

Seigou Yukutake

Shigeru Takahashi

Suguru Tachibana

Katsuhiro Shimohigashi

Takahiro Yamashita

Masayuki Kojima

Shinichi Yoshioka

Toshiaki Masuhara

Yukio Arima

Sadayuki Morita

Kunihiro Komiyaji

Kazumasa Yanagisawa

Kazuo Yano

Osamu Nishii

Hirokazu Aoki

Yonetaro Totsuka

Shoji Hanamura

Seiichi Nagata

Masakazu Aoki

Shoji Shukuri

Takashi Hashimoto

Kenichi Kuroda

Toshio Sasaki

Akihiro Shimizu

Yoshio Sakai

Yasuko Yoshida

Norio Nakagawa

Tetsuro Honmura

Takeshi Sakata

Satoru Hanzawa

Yusuke Kanno

Masaru Kokubo

Eiji Takeda

Nobuhiro Oodaira

Takashi Nishida

Kazuyuki Suko

Hiroshi Toyoshima

Yoshikazu Saitou

Kyoichiro Asayama

Fumiyuki Kanai

Keijiro Uehara

Yasuo Kiguchi

Takao Watanabe

Takayuki Kawahara

Toshihiko Tanaka

Norio Hasegawa

Yoshinobu Nakagome

Norio Suzuki

Hiroaki Suzuki

Shigeki Ohbayashi

Tokuo Kure

Osamu Ozawa

Ikuya Kawasaki

Fumio Arakawa

Yoshifumi Kawamoto

Yoshihiko Yasu

Naohiko Irie

Tetsuya Nakagawa

Ryo Mori

Masafumi Onouchi

Kazuo Otsuga

Yasuto Igarashi

Yasuhiro Sugawara

Takashi Kuraishi

A logic circuit in a system LSI (Large Scale Integrated Circuit) is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM (Static Random Access Memory) circuit of the system LSI controls a substrate bias to reduce leakage current.

Lower-power semiconductor memory device

Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage

A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Semiconductor device

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Semiconductor integrated circuit device

A semiconductor device having static memory cells is designed to reduce leakage current and power consumption. The static memory cells are coupled to word lines and bit lines, and the word lines are coupled to word drivers. A first P channel MOS transistor (MOS power switch) has a gate coupled to receive a first control signal, and a second P channel MOS transistor (MOS power switch) has a gate coupled to receive a second control signal different from the first control signal. Source-drain paths of the first and second P channel MOS transistors (MOS power switches) are coupled to respective voltage supply points for different parts of the semiconductor device, such as voltage supply points for the memory cells and the word drivers, or voltage supply points for a logic circuit and the word drivers.

Low power semiconductor memory device

Low-power semiconductor device

The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Semiconductor integrated circuit device with reduced leakage current

A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NWand are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.

Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array

A semiconductor device is provided. The semiconductor device includes a logic circuit, an SRAM circuit coupled to a power line, and a switch coupled between the logic circuit and the power line. Before the switch is changed to an off position, a part of information held in the logic circuit is transferred to the SRAM circuit.

Semiconductor device with logic circuit, SRAM circuit and standby state

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Warabi, Japan

Koichiro Ishibashi