Nec Corporation

Olympus Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Koichiro Furuta

Masato Motomura

Taro Fujii

Takao Toi

Toru Awashima

Kenichiro Anjo

Noritsugu Nakamura

Yoshikazu Yabe

Hirokazu Kami

Toshiro Kitaoka

Masayuki Mizuno

Sho Shinji

Nobuki Kajihara

Takeshi Inuo

Junichi Goto

Yoshinosuke Kato

Tooru Awashima

Yoshiyuki Miyazawa

An endoscope illumination device includes: an illumination optical system including an entrance surface disposed along a circumferential direction centered on a predetermined axis and provided at one-end side in the direction of the predetermined axis, an emission surface positioned at an outermost side in a radial direction with respect to the predetermined axis and radially emitting illumination light entering from the entrance surface, a diffusion surface disposed at an intermediate position of an optical path of the illumination light between the entrance surface and the emission surface and transmitting and diffusing the illumination light; and a light emitting portion disposed closer to the one-end side than the entrance surface is and emitting, toward the entrance surface, the illumination light substantially in the direction of the axis.

Endoscope illumination device and endoscope

An illumination device according to the present invention includes a light output unit having an output end that outputs illumination light; a diffusion layer that is disposed in a circumferential direction centered on a predetermined axis and that receives the illumination light from the output end, guides the illumination light while diffusing the illumination light, and outputs the illumination light from a surface thereof; and a reflective layer that is provided adjacent to a surface of the diffusion layer at an inner side in a radial direction and that reflects the illumination light outward in the radial direction. The diffusion layer contains a light guide material that guides the illumination light and a diffusion material dispersed and supported in the light guide material.

Illumination device

A light with higher luminance is radiated while lights of a plurality of different wavelengths are appropriately selected and light guiding efficiency is improved. An illumination apparatus including three or more light sources which are arranged so that optical axes of the light sources intersect at one point and which respectively emit lights of different wavelength ranges, an optical device which transmits a light from one of the light sources while reflecting lights from the other light sources so as to make the lights enter an optical path of the light from the one of the light sources, and an optical device rotator which rotates the optical device in a direction in which the light sources are arranged.

Illumination apparatus

An illumination device includes a light output unit having an output end; an optical member that is disposed in a circumferential direction centered on a predetermined axis and that receives illumination light output from the output end and outputs the illumination light from a surface thereof; and a reflective layer that is provided adjacent to a surface of the optical member at an inner side in a radial direction and that reflects the illumination light outward in the radial direction. The optical member includes, in order from one end in a direction along the axis, a light guide layer and a diffusion layer. The light guide layer receives the illumination light from the output end in the direction along the axis and guides the illumination light. The diffusion layer receives the illumination light from the light guide layer and guides the illumination light while diffusing the illumination light.

An illumination device includes a light output unit having an output end; an optical member that is disposed in a circumferential direction centered on a predetermined axis and that receives illumination light output from the output end and outputs the illumination light from a surface thereof; and a reflective layer that is provided adjacent to an inner side surface of the optical member and that reflects the illumination light outward in the radial direction. The optical member includes a light guide layer that receives the illumination light from the output end and that guides the illumination light and a diffusion layer that is located outside the light guide layer in the radial direction and at one end of the light guide layer in a direction along the axis and that receives the illumination light from the light guide layer and guides the illumination light while diffusing the illumination light.

The invention provides a light source apparatus including first and second light sources that output light in mutually opposing directions along a single optical axis; a wavelength conversion element that is disposed between these light sources and that generates light of a wavelength different from that of said light due to irradiation with the light; a first optical member that is disposed between the wavelength conversion element and the first light source, that transmits the light therefrom, and that reflects back light that is scattered towards the first light source, toward the wavelength conversion element; and a second optical member that is disposed between the wavelength conversion element and the second light source, that transmits the light therefrom, and that deflects, in a direction intersecting the optical axis, the light scattered toward the second light source and the light reflected back by the first optical member.

Light source apparatus

A reconfigurable device comprises a plurality of processing elements, a main memory unit that stores plural pieces of circuit configuration information, a cache unit that caches circuit configuration information forwarded to at least one of the processing elements from the main memory unit, and a cache control unit that controls forwarding of circuit configuration information from the cache unit to the processing element. The cache control unit selects circuit configuration information which must be forwarded to each processing element. When the selected circuit configuration information is not stored in the cache unit, the cache control unit reads out the circuit configuration information from the main memory unit, stores the read-out circuit configuration information in the cache unit, and sends forward the circuit configuration information to the processing element from the cache unit.

Reconfigurable device

A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N&#x2212;1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.

Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium

A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.

Array-type processor having plural processor elements controlled by a state control unit

A display device and an electronic apparatus equipped with such a display device are provided. The display device includes a liquid crystal display that displays an image; normal-illumination LEDs that emit illumination light and a partial-illumination LED that emits illumination light; a light guide unit having a first incidence surface and a second incidence surface, and configured to optically guide the illumination light received by the first incidence surface to the entire surface of the liquid crystal display and to optically guide the illumination light received by the second incidence surface to a predetermined region having the same aspect ratio as the liquid crystal display; and a switch button used for switching the size of the image displayed on the liquid crystal display to the size corresponding to the entire surface or the size corresponding to the predetermined region.

Display device and electronic apparatus equipped with the same

Configuration codes for implementing a plurality of circuits having different attributes are generated and stored in a memory for each task executed in a reconfigurable device. When the reconfigurable device is operated, an appropriate circuit to be executed by the reconfigurable device is selected in accordance with an operation state of the system from among a plurality of circuits having different attributes, and the configuration code for implementing the selected circuit is loaded from the memory into the reconfigurable device.

Information processing apparatus and method for using reconfigurable device

A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.

Data processing system for debugging utilizing halts in a parallel device

A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.

Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix

An arrayed processor has a plurality of processing elements each having a plurality of types of arithmetic logic units for processing data having different numbers of bits from one another. The arrayed processor divides a series of processing data of various numbers of bits supplied from an external circuit into data of more bits and data of fewer bits. These data are processed in parallel by the arithmetic logic units of the processing elements. The efficiency of arrayed processor can be increased, since small-scale processing operations are individually performed by the processing elements and connections between the processing elements are made according to object codes.

Processor having array of processing elements whose individual operations and mutual connections are variable

An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.

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Tokyo, Japan

Koichiro Furuta