Sharp Kabushiki Kaisha Corporation

Koichiro Fujita

Kenichi Tanaka

Naoki Takahashi

Satoshi Morishita

Tomotoshi Satoh

Hiroyuki Komeda

Katsuhiko Kishimoto

Takao Kinoshita

Yushi Inoue

Yoshimi Tanimoto

Akihiro Nishigaki

Tadashi Yasui

Tsuyoshi Nakahira

Masaharu Yamashita

Hiroki Kanai

Naomichi Fujii

Yutaka Nakayama

Junichiroh Koyama

Daisuke Kurita

A power module includes a power circuit which includes one or more power semiconductors; and a control circuit which supplies a gate signal to each of the one or more power semiconductors. The control circuit includes one or more gate drivers which generate the gate signal in accordance with a control signal and in which a side to which the control signal is input and a side on which the gate signal is generated are insulated, a control input circuit to which the control signal is input and which supplies the control signal to the one or more gate drivers, and a control output circuit which supplies the gate signal to each of the power semiconductors.

Power module

A switching control circuit that controls on/off of a switching element is provided to efficiently disperse EMI noise due to high-speed switching, the switching control circuit includes a gate driver, a variable capacitance element connected to a gate of the switching element, and a capacitance changing circuit that randomly changes a capacitance of the variable capacitance element.

Switching control circuit

In a power semiconductor module, a first conductive layer including first to fourth electrodes are formed on one of principal surfaces of an insulating layer, and a conductive substrate functioning as a second conductive layer is formed on the other one of principal surfaces. Current paths are switched by controlling switching of a first transistor and a second transistor disposed on a surface of the first conductive layer thereby performing a power conversion. A capacitor is connected, in a region, between the first electrode and the second electrode. When a current flows in the region through the second conductive layer, a charging/discharging current occurs in the capacitor, which results in magnetic field cancellation.

Power semiconductor module, electronic device, and method for controlling power semiconductor module

In a nitride-semiconductor field-effect transistor, an end on a recess side of a first insulating film is separated by a distance from an opening edge of the recess and an end on a recess side of a second insulating film is separated by a distance from the end on the recess side of the first insulating film. A part of a drain electrode out of the recess stretches toward a gate electrode side in an eaves shape, is formed over surfaces of the nitride semiconductor laminate, the first insulating film, and the second insulating film from the recess, and contacts the surfaces of the nitride semiconductor laminate, the first insulating film, and the second insulating film.

Nitride-semiconductor field-effect transistor

A nitride semiconductor device includes a substrate; a nitride semiconductor multilayer structure which is formed on the substrate, includes a first nitride semiconductor layer and a second nitride semiconductor layer having a different composition from that of the first nitride semiconductor layer, and generates two dimensional electron gas on a hetero interface between the first nitride semiconductor layer and the second nitride semiconductor layer; and an insulating film which covers at least a portion of a surface of the nitride semiconductor multilayer structure, has a concentration of Si&#x2014;H bonds equal to or less than 6.0&#xd7;10cm, and is formed of silicon nitride.

Nitride semiconductor device

A nitride semiconductor device includes a substrate, a nitride semiconductor laminate, and an ohmic electrode of TiAl-based material. The nitride semiconductor laminate has a first nitride semiconductor layer on the substrate, and a second nitride semiconductor layer forming a heterointerface with the first nitride semiconductor layer. The nitride semiconductor device has an oxygen concentration profile in a depth direction of the device across between the ohmic electrode and the nitride semiconductor laminate. The profile has a first oxygen concentration peak near an interface between the ohmic electrode and the nitride semiconductor laminate in a region, of the nitride semiconductor laminate, that is on a substrate side of the interface, and a second oxygen concentration peak having an oxygen concentration of 3&#xd7;10cm-1.2&#xd7;10cmin a position deeper than that of the first oxygen concentration peak.

A nitride semiconductor device is provide that can reduce contact resistance of an ohmic electrode and a nitride semiconductor layer. In a GaN HFET, recesses () are formed in a nitride semiconductor multilayer body () composed of an undoped GaN layer () and an undoped AlGaN layer () formed on an Si substrate (), and a source electrode () and a drain electrode () are formed in the recesses (). In a region deeper than an interface (S, S) between the GaN layer () and the source electrode () and drain electrode (), which are formed from a TiAl material, a first chlorine concentration peak (P) is formed in vicinity of the interface, and a second chlorine concentration peak (P) having a chlorine concentration of 1.3&#xd7;10cmor lower is formed at a position deeper than the first chlorine concentration peak (P).

A heterojunction bipolar transistor comprising a collector layer of a first conductivity type, a base layer of a second conductivity type, and an emitter layer of the first conductivity type, which are formed on a semiconductor substrate in this order, and further a collector electrode directly or indirectly connected to the collector layer, a base electrode directly or indirectly connected to the base layer, and an emitter electrode directly or indirectly connected to the emitter layer, wherein a semiconductor protecting layer is formed on the base layer and extended outside an edge of the base layer, the base electrode is formed on the semiconductor protecting layer, and at least a region under the semiconductor protecting layer is filled with an organic insulator.

Heterojunction bipolar transistor and production process therefor

A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over the base layer, and (c) then subjecting the base layer to thermal annealing at a temperature of 520&deg; C. to 650&deg; C.

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Sakai, Japan

Koichiro Fujita