Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Koichiro Aoki

Yoji Nishio

Tsutomu Hara

Toshio Sugano

Atsushi Hiraishi

Masahiro Yamaguchi

Yutaka Uematsu

Hideki Osaka

Seiji Funaba

An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TLfrom the data transferring element to a first branch point Swhere a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TLfrom the first branch point Sto a second branch point Swhere a second branch line is branched. A wiring length TLfrom the second branch point Sto a third branch point Swhere a third branch line is branched is configured to become greater than the wiring lengths TLand TL

Apparatus having a wiring board and memory devices

Address line wiring structure and printed wiring board having same

Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor deviceincludes plural memory chipsstacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal Lis connected to data strobe signal (DQS) pad of first memory chip. Inverted data strobe signal line for /DQS signal Lis connected to inverted data strobe signal (/DQS) pad of second memory chip

Stacked semiconductor device

Growing community of inventors

Tokyo, Japan

Koichiro Aoki