Seiko Instruments Inc

Ablic Inc.

Sii Semiconductor Corporation

Koichi Shimazaki

Tomomitsu Risaki

Shoji Nakanishi

Yoshitsugu Hirose

Hitomi Sakurai

A semiconductor device has a bonding pad and a wiring layer formed on an insulating film. The wiring layer is spaced from the bonding pad by a gap. A passivation film covers the bonding pad and the wiring layer and fills the gap. The gap has a width equal to or larger than the thickness of the passivation film, and equal to or smaller than twice a side wall thickness of the passivation film covering a side wall of the wiring layer. The semiconductor device has a high resistance to stress during bonding.

Semiconductor device having a bonding pad

In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film of the chip. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. Vias connect the second metal film and the topmost layer metal film, and all of these vias are located outside the pad opening in plan view.

Semiconductor device and ball bonder

In order to provide a semiconductor device having high ESD tolerance, a plurality of source wirings () are formed of metal films having the same shape and electrically connect a plurality of sources () to a ground voltage wiring (), respectively, a plurality of drain wirings () are formed of metal films having the same shape and electrically connect a plurality of drains () to an input voltage wiring (), respectively, and a plurality of gate wirings () are formed of metal films having the same shape and electrically connect a plurality of gates () to the ground voltage wiring (), respectively. Further, a back gate wiring () is formed of a metal film and electrically connects a back gate () to the ground voltage wiring (), and the back gate wiring () is separated from the source wiring () formed on the source ().

Semiconductor device

In order to provide a semiconductor device having high ESD tolerance, a semiconductor device (IC) is formed so that: a ground voltage wiring () is electrically connected at one end in a wiring direction thereof to a wiring () extending from a ground voltage pad used for external connection; an input voltage wiring () is electrically connected at one end in a wiring direction thereof to a wiring () extending from an input voltage pad used for external connection; and the one end of the ground voltage wiring () and the one end of the input voltage wiring () are substantially opposed to each other across a center of an NMOS transistor ().

A semiconductor device has a semiconductor substrate provided with a scribe region and an IC region. A first insulating film is disposed on the semiconductor substrate across the scribe region and the IC region. At least one separation groove is provided in the first insulating film in the scribe region. Side walls made of a plug metal film are formed only on respective lateral walls of the separation groove so that the plug metal film on the lateral walls does not extend out of the separation groove and does not exist on an upper surface of the first insulating film. A second insulating film covers at least the side walls formed on the respective lateral walls of the separation groove so that the side walls are disposed under the second insulating film.

Semiconductor device and manufacturing method therefor

Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n&#xb1; layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

Growing community of inventors

Chiba, Japan

Koichi Shimazaki