Nec Electronics Corporation

Koichi Sawahata

Noriyuki Kodama

Morihisa Hirata

An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply. The second high concentration second conductive type region is set to a potential different from the first power supply.

Electro-static discharge protection device

In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

MOS type semiconductor device having electrostatic discharge protection arrangement

A multifinger ESD protection element has between an input wiring to which a surge current is input and a reference-potential wiring, 2n-number (where n is a natural number of 2 or greater) of fingers Fto F. A drain resistor Rd(i=1 to 2n), NMOS transistor Tand source resistor Rsare connected serially in each finger Fin the order mentioned. A single unit Uis constructed by two mutually adjacent fingers Fand F(where j is a natural number of 1 to n). In each unit the source of one transistor is connected to the gate of the other transistor and the source of this other transistor is connected to the gate of the first-mentioned transistor. The source Sof finger Fis connected to the source Sof the next unit U. The 2n-number of fingers are connected in the form of a ring.

Multifinger-type electrostatic discharge protection element

The results of conventional analytical ion implantation simulation for the point defect distribution, for a silicon substrate on which an oxide layer or a nitride layer is formed, differ from the results of the Monte Carlo ion implantation simulation method. According to the present invention, it is unnecessary to distinguish between layers of materials in which point defects are or are not generated when determining the point defect distribution because, although point defects do not occur in some materials, such as oxides or nitrides, layers of these materials undergo the same amount of damage by ion implantation as layers of a material in which point defects are generated, such as silicon. Therefore, in the present invention, when carrying out simulations under ion implantation conditions in which channeling is inhibited, whether for a substrate having a layer of a material in which point defects usually are not generated, such as an oxide or a nitride, or for a substrate not having a layer of such a material, the point defect distribution simulation (steps and ) uses the same distribution as for a layer of a material in which point defects are generated.

Ion implantation simulation method

A protective circuit in a semiconductor device includes a protective n-channel MOS transistor connected between the power source line and the ground line, with the gate and drain being connected together, and an n-p-n transistor having a base connected to the source of the protective n-channel MOS transistor and connected between the power source line and the ground line. The protective circuit disposed in a low-voltage semiconductor device has a lower power dissipation due to a low junction leakage current.

Growing community of inventors

Kanagawa, Japan

Koichi Sawahata