Ssd Company Limited

Koichi Sano

Shuhei Kato

Koichi Usami

An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal 'CDSZ') indicative of the size of data to be read or written. A state machinegrants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data. Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machinecan set an optimal number of bus cycles.

Data processing unit and bus arbitration unit

A sound processor is formed on a single semiconductor device and has a function as a bus master for a common bus to positively and effectively access a resource on a common bus. Outputted is data over N sets (N being a natural number greater than 2) of sound channels through time division multiplexing to M sets (M being a natural number) of independent digital/analog converting means for converting sound-channel digital data into an analog sound signal. This reproduces pulse-code-modulated sound waveform data capable of simultaneously reproducing over a plurality of sets of sound channels represented by a product of M and N.

Sound processor

An information processing apparatus includes man-machine interface, a semiconductor memory and an information processor. The semiconductor memory is configured by an application software contents portion, an application software engine, an operating system, an information processor hardware driver and a man-machine interface driver. Clear definition is given to interfaces between modules including software and hardware.

Information processing apparatus connected to home TV set in use

A high-speed processor system having a bus arbitration mechanism constructed on a single semiconductor chip. The processor system comprises at least one bus master, a plurality of buses and a plurality of bus slaves. Each bus comprises an independent address bus, an independent data bus and individual data transfer capability. Every bus master comprises a plurality of independent bus interfaces each connected to one of the buses. Each bus slave is connected to a bus that has corresponding data transfer capability. For a system having more than two bus masters, the system further comprises a plurality of bus arbitrators for arbitrating the access of each bus independently. The bus arbitrator receives a bus request signal from each bus master that requests the bus access and issues a bus grant signal to the bus master allowed to access the bus. The bus arbitrator comprises a plurality of priority order information storage devices for storing priority order information for all the bus masters connected to the bus. At every bus cycle, one set of priority order information is selected continuously and cyclically. When more than one bus master requests the bus access at the same time, the bus arbitrator determines which bus master may access the bus according to selected priority order information.

High-speed processor system having bus arbitration mechanism

A color graphic processor generating a picture screen formed by a two-dimensional pixel array for a raster-scan display. The color graphic processor comprises a scan image generator and a color video encoder. A circular pixel buffer having a plurality of pixel buffer units is used to buffer pixel data for drawing and displaying. The pixel buffer unit storing the pixel information of a current scanning position is circularly reused after the scanning position moves to the next one. The number of pixel buffer unit is flexible and does not have to be the same as the number of pixels in a horizontal scan line. A transparent information storage means and a transparent controller are included to reduce the size of the pixel buffer and control transparent pixels. The color video encoder processes digital luminosity, saturation and hue signals according to a video sync signal and a color burst flag signal to generate a digital luminosity signal and a digital chromaticity signal. The two video signals are combined to form a composite video signal. Digital-to-analog converter converts the digital video signals to analog video signals. The color video encoder supports both NTSC and standard.

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Kusatsu, Japan

Koichi Sano