Hitachi, Ltd.

Hitachi Computer Electronics Co., Ltd.

Koichi Okazawa

Tetsuya Mochida

Nobukazu Kondo

Kazushi Kobayashi

Ichiharu Aburano

Koichi Kimura

Hitoshi Kawaguchi

Seiji Kaneko

Hideaki Gemma

Ryuichi Hattori

Takehisa Hayashi

Hideki Osaka

Takashi Oeda

Toshihiko Ogura

Tsutomu Hara

Tsunehiro Tobita

Tetsuhiko Okada

Kazuhiko Komori

Toshiaki Tarui

Yasuyuki Okada

Masaya Umemura

Takashi Moriyama

Yasuo Kurosu

Yukihiro Seki

Yoshihiro Yokoyama

Shigemi Adachi

Kouichi Nakai

Hiroaki Aotsu

Toshio Okochi

Hideya Akashi

Toru Shonai

Nobuaki Izuno

Hidefumi Masuzaki

Kenichi Saitou

Tamon Masimo

Masami Jikihara

Kensuke Ooyu

Masahide Tsuboi

Takeshi Aoki

Michinori Naitoh

Masumi Terao

Hiroshi Murashima

A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Bus system for use with information processing apparatus

In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Data processing apparatus and network system that outputs quality of service information to a user

In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Bus control system

An information processing apparatus with a hierarchized bus structure having a system bus connected to central processing units and cache memories and an I/O bus connected to I/O devices. In response to a DMA request from the I/O device, a memory controller connected to both buses and to a main memory compares previous snoop addresses stored in a buffer memory of the memory controller with a current address contained in the DMA request to check whether the current DMA request is coincident with the past snoop process. If the comparison indicates a coincident snoop process, a snoop access process request is inhibited to be output to the system bus and cache memory. With this operation, the number of snoop accesses for DMAs to the same block of the cache memory can be reduced and a time during which the system bus is occupied can be shortened, to thereby improve the system performance.

Information processor with snoop suppressing function, memory controller, and direct memory access processing method

Information processing system, bus arbiter, and bus controlling method

A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is &ldquo;0&rdquo;, a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.

Shared memory multiprocessor performing cache coherency

Accessible network of performance index tables

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Tokyo, Japan

Koichi Okazawa