Seiko Epson Corporation

Kabushiki Kaisha Suwa Seikosha

Seiko Epson Kabushiki Kaisha

Koichi Oguchi

Eiji Natori

Kazumasa Hasegawa

Tatsuya Shimoda

Takao Nishikawa

Minoru Hosokawa

Satoru Yazawa

Mitsuo Nagata

A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.

Ferroelectric memory device

The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

Memory cell array having ferroelectric capacity, method of manufacturing the same and ferroelectric memory device

A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.

Ferroelectric memory device and method of manufacturing the same

The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance or load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.

Memory cell array having ferroelectric capacitors, method of fabricating the same, and ferroelectric memory device.

A liquid crystal display device wherein display elements are arranged in a matrix display on a substrate and the display is driven in response to external display signals is provided. The display device includes a thin film layer having a rugged diffusing surface and an opposed transparent electrode plate spaced apart from the thin film layer. A guest-host liquid crystal material including a pleochroic dye is utilized. The thin film layer may be a metal film such as, aluminum, an aluminum alloy, silver or a silver alloy having a rugged surface for providing a diffused white surface formed by vaccum evaporation, sputtering, heat-treatment, recrystallization or etching.

Liquid crystal display device having diffusely reflective picture

A matrix liquid crystal display circuit includes a selecting transistor connected to the picture element and a capacitor for each picture element of the matrix. The other picture element and capacitor terminals connect to common electrodes and the transistor gates in each row connect to a common electrode. In each column a common source line connects to the sources of the transistors and a signal sampling circuit periodically applies an image signal to the source line of each column in sequence. No amplification is used between the sampling circuit and the transistor sources. Metallic leads serve as the source lines, but other circuits and components are integrated on a common substrate.

Growing community of inventors

Suwa, Japan

Koichi Oguchi