Fujitsu Corporation

Nippon Zeon Company, Ltd.

Fujitsu Semiconductor Limited

Zeon Corporation

Fujitsu Microelectronics Limited

Idemitsu Petrochemical Co., Ltd.

Sandisk Technologies Inc.

Hitachi-high-technologies Corporation

Showa Denko K.k.

Koichi Nishimura

Shinya Fujioka

Kotoku Sato

Tomohiro Kawakubo

Yoshinori Okajima

Masao Taguchi

Masato Matsumiya

Atsushi Hatakeyama

Masato Takita

Ayako Kitamoto

Mitsuyoshi Aonuma

Yoshihiro Takemae

Shinichi Yamada

Yasurou Matsuzaki

Satoshi Eto

Masao Nakano

Kuninori Kawabata

Naoharu Shinozaki

Toshikazu Nakamura

Yasuharu Sato

Kenichi Kawasaki

Toru Koga

Shusaku Yamaguchi

Mitsuhiro Higashiho

Hideki Kano

Takeo Fukushima

Hiroko Douchi

Hatsumi Iino

Tatsuya Kawamura

Terumasa Kitahara

Satoru Isomura

Toshio Ohkawa

Toyozo Fujioka

Tatsunosuke Suzuki

Yingda Dong

Atsushi Tanaka

Deepanshu Dutta

Shigeru Fujita

Toshiya Uchida

Ken Oowada

Kaoru Mori

Toshio Ohi

Kazuo Yamane

Hirohiko Mochizuki

Tadao Aikawa

Hiroyuki Takayama

Tatsuharu Arai

Naonobu Fujimoto

Ikuo Taniguchi

Fumihiro Ikawa

Shinichiro Ikemasu

Yukihiro Nomura

Toshitaka Hiro

Kazuyoshi Nakajima

Isao Kubota

Hiroyoshi Tsuboi

Hidemasa Nagasawa

Yoshiomi Saito

Hideo Fukuda

Masumi Kurokawa

Takashi Kihara

Yasuaki Serizawa

Yoshiharu Mizuno

Tsunekichi Kuriyama

Yasuaki Toyomasu

Daisuke Tsugawa

Shinya Fujijoka

Provided is an automatic analyzer capable of replacing an insertion mechanism while suppressing occurrence of dispensing abnormality and analysis result abnormality accompanying deterioration of the insertion mechanism. Included are an insertion mechanism that is inserted into a closed container through a lid of the container; a storage unit that stores an insertion history count corresponding to a cumulative load of the insertion mechanism caused by inserting the insertion mechanism into a plurality of the containers, and an allowable insertion history count which is an allowable value of the insertion history count; and a control unit that compares the insertion history count with the allowable insertion history count and performs control to make a notification to an operator in a case where the insertion history count reaches the allowable insertion history count.

Automated analysis device

In connection with an erase operation of a block of non-volatile storage elements, a determination is made as to whether the block is partially but not fully programmed. A degree of partial programming can be determined by a pre-erase read operation which determines a highest programmed word line, or which determines whether there is a programmed storage element in a subset of word lines above a small subset of source side word lines. Since a partially programmed block will pass an erase-verify test more easily than a fully programmed block, a measure is taken to ensure that the block is sufficiently deeply erased. In one approach, an erase-verify test is made stricter by adjusting a sensing parameter when the block is partially programmed. In another approach, the block can be programmed before being erased. Or, an extra erase pulse which is not followed by an erase-verify test can be applied.

Optimized erase operation for non-volatile memory with partially programmed block

A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Semiconductor memory device and method of controlling the same

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Semiconductor memory device, and method of controlling the same

An optical film composed of a thermoplastic resin film obtained by using a melt extruding machine, characterized in that said thermoplastic resin film satisfies a relation of the formula below over the whole surface of the film when an angle made by the extruding direction of the thermoplastic resin film from the melt extruding machine and a slow phase axis at each point is &#x3b1;, and a retardation amount at each point is Re, is provided. [sin2&#x3b1;]&#xd7;[sin(&#x3c0;&#xb7;Re/550)]&#x2266;4.0&#xd7;10. According to the present invention, an optical film wherein there is no problem on a residual solvent, optical distortion is small, and there is no problem of color unevenness and color absence of a liquid crystal display obtained by using the optical film as a protective film of a polarizer is provided.

Optical film and process for producing the same

A precharge voltage generating circuit outputs any of a plurality of kinds of precharge voltages in accordance with an ambient temperature. A precharge circuit supplies the precharge voltage to a bit line during the nonaccess of a dynamic memory cell. A sense amplifier amplifies a difference between the voltage of a data signal read from the dynamic memory cell onto the bit line and the supplied precharge voltage. The precharge voltage is altered in accordance with the ambient temperature, whereby the read margin of the sense amplifier can be changed, and the worst value of the data retaining time of the memory cell can be improved. As a result, the frequency of refreshing of the memory cell can be lowered, reducing power consumption and a standby current.

Semiconductor memory having a precharge voltage generation circuit for reducing power consumption

A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode register outputs a soft reset signal when at least a value of one-bit of the register part represents a reset state. A reset signal generator outputs a reset signal for resetting an internal circuit in response to the soft reset signal. In the present invention, a system that controls the semiconductor memory is required to necessarily assign a predetermined bit with a setting command of the mode register in order to generate the soft reset signal. Accordingly, it is possible to reliably reset the internal circuit by external control.

Semiconductor memory and system apparatus

A rubber composition comprising a combination of a nitrile rubber and an epilhalohydrin rubber is cross-linked to give a crosslinked product, by using at least two kinds of crosslinking agents selected from a sulfur-containing crosslinking agent, a mercaptotriazine crosslinking agent and a 2,3-dimercaptoquinoxaline crosslinking agent.

Crosslinkable rubber composition

Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

Variable digital delay line

Denitrated combustion exhaust gas is desulfurized with ammonia, the waste water obtained from washing the desulfurization waste water or dust ash is filtered using calcium carbonate, the pH of the filtrate is adjusted, carbon dioxide and/or aqueous carbonic acid is added and then a flocculating agent is added, and ammonia is recovered from the supernatant after precipitation and separation of the solid portion. The recovered ammonia is added to the denitrated gas for treatment of the combustion exhaust gas.

Combustion exhaust gas treatment process and treatment apparatus

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Kawasaki, Japan

Koichi Nishimura