Sharp Kabushiki Kaisha Corporation

Koichi Nishida

Kazuhisa Okada

Andrew Kay

Akihisa Yamada

A high level synthesis method for generating a logic circuit of a register transfer level from an operation description includes a control data flowgraph generation stage; a scheduling stage; an allocation stage; a data path generation stage; and a control logic generation stage. When generating a thread sharing a common memory with another thread operating in parallel therewith, a memory access request is represented by a node of a control data flowgraph so as to perform scheduling, and a control logic is generated. The control logic outputs a memory access request signal to a common memory interface in a state corresponding to a step to which the node is scheduled, and keeps the state until a memory access request acceptance signal from the common memory interface is changed to be active.

High level synthesis method, thread generated using the same, and method for generating circuit including such threads

A high-level synthesis method comprising the steps of converting an operating description describing one or more operations to a control data flow graph (CDFG) including one or more nodes representing the one or more operations and one or more I/O branches representing a flow of data, scheduling the CDFG obtained by the converting step, and allocating one or more logic circuits required for executing the CDFG obtained by the scheduling step. A portion of the CDFG in the converting step is subjected to logical synthesis in advance to generate a node, and the portion of the CDFG is replaced with that node.

High-level synthesis method and storage medium storing the same

The present invention relates to a scheduling method and apparatus for high-level synthesis of a circuit which is represented by an operation description. The method includes calculating a probability for each of a plurality of nodes included in a control flow graph to be assigned to a time step and calculating a sum of the probabilities for each time step. For each node having a scheduling candidate in a time step for which the sum of probabilities is maximum, an estimated value of an area of the circuit is calculated with the node having been temporarily assigned to the scheduling candidate and a combination of a node and a scheduling candidate for which the estimated value is maximum is retrieved. Finally, a list of scheduling candidates of the node in the combination is narrowed down by excluding the scheduling candidate in the combination from the list of scheduling candidates of the node in the combination.

Scheduling method for high-level synthesis and recording medium

A circuit synthesis method includes the steps of converting a behavioral description describing a behavior of calculation processing into a control data flowgraph; assigning a plurality of calculations, at least one input and at least one output in the control data flowgraph into a plurality of prescribed time slots; assigning the plurality of calculations, a plurality of data dependency edges, the at least one input and the at least one output respectively to a plurality of calculation devices, at least one register, at least one input pin and at least one output pin; generating a plurality of paths corresponding to the plurality of data dependency edges; detecting a feedback loop formed of at least two of the plurality of paths and at least one of the plurality of calculation devices; and re-assigning one calculation, which has been assigned to a first calculation device included in the feedback loop, to a second calculation device among the plurality of calculation devices, so as to delete the feedback loop.

Circuit synthesis method

A circuit synthesis method includes the steps of converting a behavioral description describing a behavior of calculation processing into a control data flowgraph; assigning at least one calculation, at least one input and at least one output in the control data flowgraph into prescribed time slots; assigning the at least one calculation, a plurality of data dependency edges, the at least one input and the at least one output respectively to at least one calculation device, at least one register, at least one input pin and at least one output pin; generating a plurality of paths corresponding to the plurality of data dependency edges; and detecting a first false path among the plurality of paths.

A high-level synthesis apparatus for receiving operational descriptions includes synchronous communication instructions between threads which operate in parallel, and for synthesizing a product circuit based on the received operational descriptions. The high-level synthesis apparatus includes: an extractor for analyzing the received operational descriptions and extracting consecutive synchronous communication instructions which are of the same kind from among the received operational descriptions; a scheduler for generating scheduling for each thread by bundling together the extracted synchronous communication instructions into one arithmetic operation; and a circuit generator for generating the product circuit based on results of the scheduling, the product circuit being capable of commencing the bundled synchronous communication instructions with the same level of priority based on handshaking.

High-level synthesis apparatus, high level synthesis method, and recording medium carrying a program for implementing the same

A hardware synthesis method for synthesizing a hardwired circuit from a behavioral description written in a language including execution control branch instructions such as an if-goto statement and a switch statement is provided. More specifically, hardware is synthesized by converting a behavioral description including an execution control branch instruction into a control flow graph (CFG) using a branch node and a merge node, converting the CFG into a control data flow graph (CDFG), performing scheduling according to the CDFG, and executing allocation according to the result of the scheduling.

Growing community of inventors

Tenri, Japan

Koichi Nishida