Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Jujo Paper Co., Ltd.

Koichi Nagai

Katsuya Murakami

Isao Ozawa

Daisuke Hashimoto

Mitsunori Tadokoro

Teruji Yamakawa

Yutaka Kojima

Kazuo Nakashima

Shinichi Kanno

Takanori Watanabe

Yasuo Kudo

Akira Tanimoto

Hiroyo Oshima

Isao Maeda

Hiroshi Isozaki

Naoki Esaka

Isao Kano

Masaru Ishii

Satoru Fukuchi

Takashi Omori

Shinji Honjo

Ken Ishiguro

Toyohide Isshi

Yuji Kashiwagi

Kazuhiko Taira

Akihiro Kasahara

Yukio Kobayashi

Naomasa Takahashi

Manabu Matsumoto

Fumio Fujimura

Nobuhiro Kondo

Kunio Hata

Yukimasa Miyamoto

Koichi Imamura

Shoji Sawamura

Kiyotaka Uchimaru

Hidenori Sai

Ryuji Ishikawa

Youhei Shiokoshi

Yoshihiko Shimura

Hiroyasu Nakatsuka

Yaotung Kuo

According to one embodiment, a controller of a memory system manages a current extended pointer that includes a pointer and cycle counter. The controller identifies, for each time the first time elapses, a first time range whose an end time matches a time that is prior to a specific time from a current time. The controller acquires a first extended pointer stored in a first entry among the plurality of entries that corresponds to the first time range. The controller identifies one or more commands stored in the first queue within the first time range by using the first extended pointer. The controller aborts the identified one or more commands.

Memory system

According to one embodiment, an information processing system includes a host and memory systems. A first memory system stores first data in a nonvolatile memory. A second memory system stores second data in a nonvolatile memory. The host transmits first update data to the first memory system and transmits second update data to the second memory system. The first memory system generates first XOR data by performing an XOR operation on at least the first data and the first update data, and transmits the first XOR data to the second memory system. The second memory system generates second XOR data by performing an XOR operation on the second data, the second update data, and the first XOR data, and transmits the second XOR data to a third memory system.

Information processing system controlling multiple memory systems

According to one embodiment, a memory system includes a non-volatile memory with a plurality of blocks. The minimum unit of a data erasing operation in the memory system is a block. A controller is electrically connected to the non-volatile memory and configured to execute, in response to a first command from a host requesting a secure erase of secure erase target data stored in a first logical area identified by a first logical area identifier, a copy operation copying valid data other than any secure erase target data from one or more first blocks of the plurality in which the secure erase target data is stored to one or more copy destination blocks of the plurality. The controller executes the data erasing operation on the one or more first blocks after the copy operation.

Memory system and control method

According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.

Information processing apparatus

According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.

Memory system and method of controlling nonvolatile memory

According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores first data in the nonvolatile memory, performs a first transmission of a write request associated with the first data to the memory system, and stores management data including information equivalent to the write request in the nonvolatile memory. In response to receiving a first response to the write request transmitted in the first transmission, the CPU adds, to the management data, information indicating that the first response has been received. The CPU deletes the first data and the management data in response to receiving a second response to the write request transmitted in the first transmission after receiving the first response.

According to one embodiment, a data storage apparatus includes a controller with a data protection function. The controller manages first and second personal identification data. The first personal identification data only includes authority to request inactivation of the data protection function. The second personal identification data includes authority to request inactivation of the data protection function and activation of the data protection function. The controller permits setting of the first personal identification data, when the second personal identification data is used for successful authentication and the first personal identification data is an initial value, or when the data protection function is in an inactive state.

Data storage apparatus, data processing system, and data processing method

According to one embodiment, an information processing apparatus includes a connector to which a storage device is connectable. The apparatus includes a power supply circuit which supplies power to the storage device via one or more power pins of the connector. The first pin of the connector is set to a first electric potential or an open state based on a power supply capability of the power supply circuit. A state of the first pin which is set to the first electric potential indicates that a maximum power supplied from the power supply circuit to the storage device via the one or more power pins of the connector is a first power. A state of the first pin which is set to the open state indicates that the maximum power is a second power.

Information processing apparatus and storage device

According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.

Semiconductor device and semiconductor package including plural solder ball sets each corresponding to a pair of differential input and differential output signals

According to one embodiment, a memory device includes: a nonvolatile semiconductor memory; and a controller which controls the semiconductor memory. The controller includes: a first memory which stores a first key; a second memory which stores a second key; a first generator which generates a third key based on a random number; a second generator which generates a fourth key based on the first key and the third key; and an encryptor which encrypts the second key with the third key. The third key and the encrypted second key are stored in a host device enabled to access the memory device.

Memory device and host device

Growing community of inventors

Tokyo, Japan

Koichi Nagai