Hitachi, Ltd.

Koichi Motohashi

Yutaka Kobayashi

Masahiro Iwamura

Tatsumi Yamauchi

Atsushi Hiraishi

Takashi Akioka

Masanori Odaka

Shigeru Takahashi

Yuji Yokoyama

Nobuo Tamba

Akira Ide

A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.

Semiconductor memory device having a redundancy capability

In a semiconductor integrated circuit device, input protective elements have current limiting resistors which are diffused resistors of a second conductivity type formed in a first semiconductor region of a first conductivity type isolated electrically by a second semiconductor region of the second conductivity type, with the first conductivity type semiconductor region being in a floating state electrically. The input protective elements create less leak current and have high electrostatic durability.

Semiconductor integrated circuit device double isolated CMOS input

Growing community of inventors

Takasaki, Japan

Koichi Motohashi