Canon Kabushiki Kaisha

Koichi Morishita

Makoto Fujiwara

Yoshiaki Katahira

Katsutoshi Ushida

Akiyoshi Momoi

Yuichi Naoi

Shunichi Kaizu

Hisashi Ishikawa

Daisuke Shiraishi

Yasuyuki Nakamura

Yasunari Nagamatsu

Koji Moriya

Makoto Fukuo

Yasuhiro Kato

Shiori Wakino

Takeshi Hiraoka

Takuya Minakawa

Mitsuhiro Inagaki

There is provided with an information processing apparatus. A plurality of functional blocks are in synchronization relationship. Each of a plurality of generation units comprises a counter and a frequency division circuit. The frequency division circuit frequency-divides a reference clock based on a value of the counter. Each of the plurality of generation units supplies a clock generated using the reference clock to a corresponding functional block among the plurality of functional blocks.

Information processing apparatus including function blocks and generation units

A bus system comprises a plurality of bus modules each for performing data transfer between a master module and a slave module. A power control module controls transition to a power-saving mode of each bus module based on communication with the plurality of bus modules. The power control module comprises a plurality of control modules corresponding to the plurality of bus modules respectively. Each control module performs communication with the corresponding bus module using power control signals.

Information processing apparatus, data transfer apparatus, and control method for data transfer apparatus

If data received by an external device controller from an external device is delayed by one cycle or more with respect to an output clock of the external device controller, a delay may not necessarily be detected with an existing configuration. When a data latch timing of the external device controller is adjusted, gating of or releasing gating of an output clock of the external device controller is performed in accordance with predetermined gating information, thus improving the accuracy of calibration for adjusting the data latch timing.

Information processing apparatus or information processing method

According to the present invention, a phase shift of data received by an external device controller is delayed and corrected, and a control signal used for the data load control on the external device controller side is delayed period-by-period. Further, the phase shift is adjusted and then the control signal is adjusted. The adjustment can beneficially be performed very quickly. Moreover, the present invention is also beneficial for preventing a failure to load data.

If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information processing apparatus may require an additional process for adjusting a data latch timing. Delay information indicating a relationship between a calibration pattern to be received and an amount of cycle delay is stored in advance. Thus, the time required for detecting an amount of cycle delay, which is equivalent to the amount by which a signal for controlling a data latch mechanism in the information processing apparatus to stop its operation is delayed, can be reduced.

Information processing apparatus or information processing method which supplies a clock to an external device

An image forming apparatus which forms a halftone image on a print medium () using multipass processing of scanning a single area on the print medium () by a printhead () N times and forming dots every scan operation includes a pass division table () used to set the print density ratio of each scan operation, a print data generation unit () which generates print data of each scan operation, a printer engine () which prints a halftone image on the print medium () on the basis of the generated print data, and a sensor () which detects the state of printing on the print medium () by the printer engine (). The print data generation unit () corrects print data in synchronism with printing by the printer engine () on the basis of the set print density ratio and the detected printing state.

Image forming apparatus and image forming method

A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter Areceives data transfer requests with respect to a slave Agenerated by masters Aand B. The arbiter Acooperates with an arbiter B, and arbitrates a contention of the data transfer requests with respect to the slave Agenerated by the masters Aand B

Bus arbitration apparatus and method

To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes an input section which executes input processing of image data read by an image reading device in accordance with the data output format of the device, an output data control section which distributes the image data that has undergone the input processing by the input section in accordance with the output format of the image reading device, an address generation section which generates address information corresponding to the output format to store the distributed image data in a memory, and a memory control section which DMA-transfers the distributed image data to the memory and stores the image data on the basis of the generated address information.

Image processing apparatus and image processing method

The remaining time period until the deadline of transfer by a device connected to a bus is measured, the remaining data size to be transferred by the device is detected, and the priority level of the device is set based on the remaining time period and the remaining data size.

Method of setting priority of devices connected to bus, and apparatus having a plurality of devices and arbiter

To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes a memory area control section which sets, for image data bitmapped on a first memory, a rectangular area divided in a main scanning direction and sub-scanning direction, an address generation section which generates address information to read out image data corresponding to the rectangular area in correspondence with the set rectangular area, a memory control section which reads out the image data corresponding to the rectangular area and DMA-transfers the image data to a second memory in accordance with the generated address information, and an image processing section which executes image processing for each rectangular area of the DMA-transferred data by using the second memory.

A bus system which transfers data from a first device to a second device includes a holding unit which holds data input from the first device, and a selecting unit which selects whether to output the data from the first device to the second device by holding the data by the holding unit or without holding the data by the holding unit.

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Tokyo, Japan

Koichi Morishita