Oki Electric Industry Co., Ltd.

Nec Corporation

Oki Semiconductor Co., Ltd.

Koichi Morikawa

Hiroaki Nakano

Kentaro Nakahara

Akira Kamei

Hiroshi Kajitani

Kenichiro Fukushi

Chenhui Huang

Toshinori Takemura

Zhenwei Wang

Hiroshi Okuda

Hannah Pokka

Yuka Imai

Itsumi Haneda

Tadashi Chiba

Itsumi Kato

A mobile terminal acquires a schedule of a user using a module device that includes a sensor, and instructs the module device to initiate a process for determining when to start or when to stop transmitting sensing information detected by the sensor to a communication destination, on the basis of the schedule. The module device acquires the sensing information, and initiates the process for determining when to start or when to stop transmitting the sensing information to the communication destination, on the basis of the instruction to initiate the determination process.

Module management system, module management method, and program

An information processing system includes an identification unit configured to identify unique information on shoes using at least part of a captured image of the shoes, and a setting unit configured to set an association between an acquisition device configured to acquire the unique information and a module device attached to the shoes based on the unique information.

Information processing system, information processing device, insole, information processing method, and recording medium

A mobile terminal detects a self-device being located at a predetermined location, and stops reception of sensing information from a module device that transmits the sensing information, if being located at the predetermined location is detected. A fixed device receives the sensing information from the module device, and transmits the sensing information to a cloud server.

Upload system, upload method, upload device, and program

A level shifter that prevents through currents thereat, including a holding circuit having an inverter made up of transistors connected between an internal node and a ground potential and an inverter made up of transistors connected between an internal node and the ground potential. These inverters are connected in loop form thereby to hold signals of nodes. Thus, even when input signals complementary to each other originally are both brought to a level 'L', the signals of the nodes are held at the immediately preceding level, thus making it possible to prevent through currents from flowing through the transistors respectively.

Level shifter

A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is pulled up between the pair of bit lines, because electrical potential at a high-level side is approximately equivalent to power potential. Accordingly, when one of adjacent bit lines is on high-level and the other is on low-level, potential difference is reduced by the pull-up, resulting in reduction of generating time of the coupling noise. Although read-out of data can not be performed while the coupling noise is being generated, since the concerned generating time is reduced in the invention, the operation speed is substantially fast.

Multi-port semiconductor memory

A semiconductor integrated circuit operating in an active state and a sleep state has a power line that is branched through a first transistor to a first virtual power line and through a second transistor to a second virtual power line. The first transistor is switched on in the active state and off in the sleep state; the second transistor is switched off in the active state and on in the sleep state. The first virtual power line powers logic circuits. The second power line powers a memory circuit that stores necessary logic-circuit signal levels during the sleep state. The memory circuit does not consume power in the active state.

Semiconductor integrated circuit with sleep memory

A semiconductor storage device in the invention comprises a first control transistor which is connected between a bit line and a first node and whose control terminal is connected to a word line, a data retention circuit which includes a first transistor that is connected between the first node and a second reference voltage terminal, as well as a first inverter that includes a second transistor connected between a second node and the second reference voltage terminal, and a substrate potential control circuit which selectively alters a substrate potential of the first transistor so as to make a threshold voltage of the first transistor higher as compared with threshold voltages of the first control transistor and the second transistor. Thus, it is permitted to provide the semiconductor storage device of static type which realizes a reduced layout area and a lower-dissipation-power operation while ensuring the reliability and high operating speed of the write and read of data.

Semiconductor storage device having substrate potential control

A content addressable memory includes a seek access circuit with four transistors connected in series between a pair of bit lines. The two inner transistors are driven by a data storage circuit; the outer two transistors function as enable transistors. A level shifting circuit receives an enable signal and shifts one or both of the logic levels of the enable signal so as to widen the potential difference between them. The shifted enable signal drives the enable transistors in the seek access circuit. Shifting the high logic level of the enable signal upward speeds up seek access by reducing the on-resistance of the enable transistors. Shifting the low logic level of the enable signal downward reduces subthreshold leakage through the seek access circuit, thereby reducing current consumption, speeding up read and write access, and preventing access errors.

Content addressable memory with shifted enable signal

A writing operation control circuit for a semiconductor memory includes a driving circuit which operates to perform a writing operation in response to a writing data signal, the driving circuit having a specific threshold voltage; a first voltage control circuit which selectively outputs first and second supply voltages to the driving circuit in response to a logical level of a write controlling signal; and a second voltage control circuit which selectively outputs third and fourth supply voltages to the driving circuit in response to a logical level of the write controlling signal. The second supply voltage is higher than the first supply voltage, the first supply voltage is higher than the fourth supply voltage, and the fourth supply voltage is higher than the third supply voltage.

Writing operation control circuit and semiconductor memory using the same

A semiconductor driver circuit includes a first inverter circuit that inverts an input voltage and supplies a first inverted voltage, and a second inverter circuit that inverts the first inverted voltage and outputs a second inverted voltage. The second inverter circuit includes a first conduction type transistor, such as a PMOS transistor, and a second conduction type transistor, different from the first conduction type transistor, such as an NMOS transistor. The driver circuit further includes a substrate voltage supply circuit that supplies voltages to the substrate of the first conduction type transistor and the substrate of the second conduction type transistor, respectively, according to the second inverted voltage, and a substrate voltage control circuit that adjusts the substrate voltages applied to either or both of the first and second conduction type transistors, according to the second inverted voltage, in order to lessen the power consumption of the driver circuit.

Semiconductor driver circuit utilizing substrate voltage control

The present invention comprises first unit cells each including PMOS transistors and NMOS transistors, each transistor having a first threshold voltage, second unit cells each including PMOS transistors and NMOS transistors, each transistor having a second threshold voltage, a unit cell array comprised of the first and second unit cells laid in array form, a power switch disposed around the unit cell array and comprised of the PMOS transistors and NMOS transistors each having the second threshold voltage, and input/output circuits disposed around the unit cell array. Another invention comprises a first power supply line supplied with a first power supply potential level, a second power supply line supplied with a second power supply potential level, a first virtual power supply line, a second virtual power supply line, a latch circuit electrically connected between the first and second power supply lines, at least one logic circuit electrically connected between the first and second virtual power supply lines, a first capacitor electrically connected between the first power supply line and the first virtual power supply line, and a second capacitor electrically connected between the second power supply line and the second virtual power supply line.

Semiconductor integrated circuit device

The invention intends to provide a semiconductor integrated circuit including MOS transistors, which is able to operate at a high-speed with a low power supply voltage in the active mode, and to reduce the power consumption resulting from the leakage current in the standby mode. In view of the foregoing object, the semiconductor integrated circuit of the invention is comprised of a first power supply line to which a first power supply potential is supplied, a virtual power supply line, a logic circuit connected to the virtual power supply line, a power control transistor provided between the first power supply line and the virtual power supply line, having a control electrode to which a first control signal is inputted, a second power supply line to which a second power supply potential is supplied, and a substrate potential control circuit connected to a substrate on which the power control transistor is formed, the first power supply line, and the second power supply line.

Growing community of inventors

Tokyo, Japan

Koichi Morikawa