Mitsubishi Denki Kabushiki Kaisha

Koichi Moriizumi

Hironobu Taoka

Kinya Kamiyama

Makoto Kanno

Hidekazu Oda

Shinichi Satoh

Masahiro Yoneda

Yoshio Kohno

Masahiro Hatanaka

Takeshi Fujino

Yusaku Ono

Susumu Takeuchi

Kazuhiro Yamazaki

Hiroomi Nakao

A finished pattern that will be formed based on a design layout pattern in a semiconductor manufacturing process is predicted, and the outline of the predicted finished pattern is converted into a polygon. On the other hand, test reference patterns are formed based on the design layout pattern. A pattern distortion in the predicted finished pattern is detected by comparing the polygonized predicted finished pattern with the test referencepatterns. In converting the predicted finished pattern into a polygon, the number of apices of the polygon is reduced. Two kinds of test reference patterns are formed: an upper limit test reference pattern obtained by reducing the design layout pattern and defining an allowable upper limit and a lower limit test reference pattern obtained by enlarging the design layout pattern and defining an allowable lower limit.

Apparatus and process for pattern distortion detection for semiconductor process and semiconductor device manufactured by use of the apparatus or process

A correction target edge extracting part of a layout pattern data correction apparatus extracts a correction target edge from circuit layout patterns. A density calculation region setting part of the apparatus sets density calculation regions around the center of the correction target edge. An area density calculating part calculates an area density of design patterns within the density calculation regions. Given the area density thus calculated, a correction pattern size calculating part calculates the size of a correction pattern to be superposed on the correction target edge. In accordance with the calculated size, a correction pattern generating part generates the correction pattern. A graphic calculating part adds up the correction pattern and design layout patterns to generate corrected layout patterns.

Apparatus and method for inhibiting pattern distortions to correct pattern data in a semiconductor device

A electron beam writing data creating device comprises a redundant part split means for splitting data into a redundant part formed by connecting redundant areas of graphic data processing areas with each other and an internal area defined in the graphic data processing area by the outer periphery of the redundant area. The redundant part split means splits design layout data into the redundant part and the internal area, for independently performing overlap removal processing in each area. Thus, a electron beam writing data creating device capable of effectively suppressing deterioration of dimensional accuracy of a writing pattern can be provided.

boundary processing of oblique overlapping graphics to achieve dimensionally accurate electron beam irradiation

A method of producing charged beam drawing data includes a basic figure processing step of performing a basic figure processing to design layout data to output basic figure data, a first segmenting step of converting the basic figure data as if segmenting a basic figure over a boundary of a figure processing region in the basic figure data by the boundary, a first searching step of searching a minute figure to draw which satisfies a prescribed size condition among the figures produced by segmenting in said first segmenting step, a restoring step of integrating the minute figure to draw searched by said first searching step and a figure adjacent to the minute figure, and performing a further basic figure processing to restore the figures in said basic figure data, an allocating step of allocating the figures restored by said restoring step to drawing fields, and a step of converting the figures allocated by the allocating step to charged beam drawing data.

Method of producing highly precise charged beam drawing data divided

A pattern comparison inspection system includes: an occupancy calculating portion for dividing pattern data into pixel regions and calculating a ratio of divided pattern data to a pixel region; a gray level bit map generating portion for generating a gray level bit map based on the ratio of the divided pattern data; and a bit map comparing portion for making a comparison between a gray level bit map for design pattern data and a gray level bit map for pattern data for an electron beam patterning system both generated by the occupancy calculating portion and the gray level bit map generating portion to determine whether the pattern data for an electron beam patterning system matches the design pattern data.

Pattern comparison inspection system and method employing gray level bit

A charged beam pattern data generating method for generating high quality pattern data from the circuit layout design data of a semiconductor device for use by a charged beam drawing apparatus in the production of resist patterns or other semiconductor device manufacturing processes.

Charged beam pattern data generating method and a charged beam pattern

A system for preventing deterioration of dimensional accuracy by reducing production of micro graphics at the time of production of drawing data to be input to a charged particle beam drawing apparatus. A CPU divides a design layout data into units of graphic data processing area (a step S1) and executes elimination of duplication and tone reversal processes in both X direction and Y direction (steps S2A, S2B) for the respective graphic data processing areas. Moreover, it performs, with reference to a micro graphic dimensional value, the graphic data processing result judging and selecting function in both the X direction and Y direction (a step S3) for the respective graphic data processing areas. Namely, the CPU judges as the micro graphic when the dimension of a basic graphic after the elimination of duplication and tone reversal processes is no larger than the micro graphic dimensional value, compares the two by determining the sum of such micro graphics, for example, in the X, Y directions and selects the graphic data submitted to the elimination of duplication and tone reversal process for the direction with smaller value. The CUP further performs prescribed processing (steps S4, S5) of this graphic data to complete the production of drawing data.

Charged particle beam drawing data production apparatus and charged

An electron-beam exposure apparatus includes a sample stage for holding a sample, an electron gun, a first aperture for shaping an electron beam emitted from the electron gun, an electro-optical device for causing an electron beam formed by the first aperture to be deflected and to be converged on a sample held on the sample stage, a second aperture in which a plurality of block patterns are formed, for shaping an electron beam from an electro-optical device, and a movement device for moving the second aperture in order to cause an electron beam from the electro-optical device to strike a desired block pattern among a plurality of the block patterns.

Electron-beam exposure apparatus

An electron beam exposure method incorporating a proximity effect correction for a pattern including large-area drawing patterns and small-area drawing patterns. The method includes dividing each large-area drawing pattern into a plurality of unit patterns and calculating the optimum electron beam exposure for each unit pattern and for each small-area drawing pattern. The calculation includes a proximity effect correction for each unit pattern and each small-area drawing pattern adjacent unit patterns having the same calculated exposures are merged into larger areas and drawing data based on the merged unit patterns, the unit patterns not merged, and the small-area drawing patterns is generated. The pattern is exposed to an electron beam that is controlled in accordance with the drawing data.

Electron beam exposure method

A method of preparing drawing data for a charged beam exposure system includes: constructing, from pattern data having a multiple hierarchical structure, reiterative units disposed in an array without any gap formed therebetween; converting the pattern data into first figure processing data including a total figure and reiterative units within the total area; dividing the total area of the first figure into equal area processing data fields for a charged beam exposure system, each field including a whole number of reiterative units, if any, thereby producing second figure processing data; performing figure modification processing with respect to features in a field outside reiterative units in the field and separately with respect to the reiterative units within the field, thereby producing third figure processing data; and converting the third figure processing data into suitable drawing data for the charged beam exposure system.

Method of preparing drawing data for charged beam exposure system

A dynamic type semiconductor device comprises a memory cell array including a plurality of cell groups, each of the cell groups including four adjacent memory cells disposed in a point symmetry fashion, with a single contact hole formed at the center of the point symmetry to be common to the four memory cells, in which the four memory cells and bit lines are connected through the single contact hole.

Semiconductor memory cells having common contact hole

A semiconductor memory device comprises four memory cells (4a, 6) arranged in point symmetry on a semiconductor substrate (1), and an insulating layer (10) covering the memory cells and having one contact hole (2) placed in the center of the point symmetry, with the contact hole enabling electrical connection to each of the memory cells.

Semiconductor memory device

A charged beam pattern defect inspection apparatus for inspecting pattern defects on materials such as masks or wafers comprising: a collecting charged beam irradiation apparatus including scanning deflection device for accelerating and focusing the scanning beam, and a detector for detecting phenomenon produced by incident particles such as reflected electrons, secondary electrons, cathodeluminescent light, X rays, or absorption currents; a scanning and synchronous signal generator for generating a scanning signal to be control the scanning deflection means and a synchronous signal to fed into an A/D converter; a two-dimensional video memory including an A/D converter and an address signal generator; a video signal operator for operating the video signal stored in the two-dimensional video memory; a stage driving apparatus for driving a stage for holding the material to be inspected, which includes a position detector for detecting the position of the stage; an auxiliary memory device for storing inspection data; and a control operation apparatus for controlling the scanning and synchronous signal generator, the two dimensional video memory, the video signal operator, the stage driving apparatus, and the auxiliary memory device, and for outputting the output of the video signal operator as the result of pattern defect inspection.

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Hyogo, Japan

Koichi Moriizumi