Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Koichi Matsuno

Tadashi Iguchi

Naoki Kai

Yoshihiro Yanai

Yoshinori Kitamura

Kazunori Nishikawa

Shinichi Ito

Seiji Morita

Soichi Inoue

Satoshi Nagashima

Hiroshi Kawamoto

Hiroaki Tsunoda

Minori Kajimoto

Isahiro Hasegawa

Tatsuhiko Higashiki

Takeshi Sakaguchi

Kei Hattori

Seiro Miyoshi

Junichi Shiozawa

Shinichi Sotome

Yoshiaki Himeno

Tadayoshi Watanabe

Shoichi Miyazaki

Hiroaki Naito

Karin Takayama

Kenrou Kikuchi

Hirokazu Sugiyama

Yoshihisa Fujii

Tetsuya Kamigaki

Takashi Sugihara

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a columnar portion, a hole, and a sealing film. The stacked body includes a plurality of conductive layers stacked with an air gap interposed. The columnar portion includes a semiconductor body. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and contacts the foundation layer. The hole extends in the stacking direction through the stacked body and forms a cavity communicating with the air gap. The sealing film plugs an upper end of the hole forming the cavity.

Semiconductor device and method for manufacturing same

A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.

Semiconductor memory device and method for manufacturing same

A semiconductor device according to the present embodiment includes a plurality of wires. A plurality of wire drawing pads are provided correspondingly to the wires and electrically connecting a plurality of contacts to the wires, respectively. First space portions widen toward a first direction from the wires to the wire drawing pads and are located between adjacent ones of the wire drawing pads in a connection region between the wires and the wire drawing pads. Second space portions are provided at edge portions of the wire drawing pads. Air gaps or insulating layers are provided in the first space portions and the second space portions.

Semiconductor device and manufacturing method thereof

According to an embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor layer; a first gate insulating film; a plurality of floating gate electrodes; a second gate insulating film; a plurality of control gate electrodes; and an upper insulating film. The semiconductor layer is provided on a substrate and extends in a first direction. The floating gate electrode is formed on the semiconductor layer via the first gate insulating film. The control gate electrode faces the upper surface of the floating gate electrode via the second gate insulating film. Moreover, the control gate electrode extends in a second direction intersecting the first direction. The upper insulating film is formed on an upper portion of the plurality of control gate electrodes. Moreover, a height of an upper surface of the upper insulating film changes along the second direction.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to an embodiment, a nonvolatile semiconductor memory device comprises a memory area, a capacitor area, and a transistor area, on a semiconductor substrate. The nonvolatile semiconductor memory device comprises a memory cell and a select gate transistor, in the memory area. The nonvolatile semiconductor memory device includes a capacitor comprising a first electrode layer and a second electrode layer stacked on the first electrode layer via an insulating layer. An upper surface of the capacitor is covered by a first insulating layer, and the insulating layer has an upper level portion and a lower level portion. A part of an outline of the upper level portion is along a part of an outline of the second electrode layer.

Method of manufacturing a semiconductor device includes forming, in a first region, a first trench through a second gate electrode film and an interelectrode insulating film, and a second trench partially extending into a sacrificial film in an isolation trench, filling the second trench with a first insulating film; forming a third gate electrode film above the second gate electrode film and into the first trench such that the third gate electrode film contacts the first gate electrode film; etching the third and the second gate electrode film, the interelectrode insulating film, and the first gate electrode film to form select gate electrodes in the first region and a group of memory-cell gate electrodes in the second region; removing the sacrificial film; and forming a second insulating film over the element regions and the isolation trench to define an unfilled gap in the isolation trench below the memory-cell gate electrodes.

Method of manufacturing semiconductor storage device and semiconductor storage device

A semiconductor device including a first isolation region dividing a semiconductor substrate into first regions; memory cells each including a tunnel insulating film, a charge storing layer, an interelectrode insulating film, and a control gate electrode above the first region; a second isolation region dividing the substrate into second regions in a peripheral circuit region; and a peripheral circuit transistor including a gate insulating film and a gate electrode above the second region. The first isolation region includes a first trench, a first element isolation insulating film filled in a bottom portion of the first trench, and a first gap formed between the first element isolation insulating film and the interelectrode insulating film. The second isolation region includes a second trench and a second element isolation insulating film filled in the second trench. The first and the second element isolation insulating films have different properties.

Semiconductor storage device and method of manufacturing the same

In general, according to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region and a peripheral region. The memory cell region includes first element isolation regions, first semiconductor regions, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. The first element isolation regions separate a semiconductor layer and include a first insulating film. The first semiconductor regions are separated by the first element isolation regions. The peripheral region includes a second element isolation region a second insulating film. Each of the first element isolation regions includes a first and a second portion. A step is present between the first and the second portion. At least part of a side surface and a lower end of the second element isolation region are surrounded by the semiconductor layer.

Nonvolatile semiconductor memory device and method for manufacturing the same

A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A memory cell array includes a plurality of memory cells provided on the semiconductor substrate in an array direction. A selection gate transistor is provided on an end of the memory cell array, and is used to select the memory cells from the memory cell arrays. A dummy cell is provided between a gate electrode of one of the memory cells on the end of the memory cell array and a gate electrode of the selection gate transistor. The width of a gate electrode of the dummy cell in the array direction of the memory cells and the dummy cell is twice or more as large as the width of the gate electrode of one of the memory cells.

Semiconductor storage device and manufacturing method thereof

According to one embodiment, firstly, an inversion pattern having a periodic pattern in which a first line pattern and a space are inversed and a non-periodic pattern arranged at an interval which is substantially equal to the width of the first line pattern from the end of the periodic pattern is formed above a processing object so as to correspond to the plurality of spaces between a plurality of first line patterns in a first pattern and the space between the first pattern and a second pattern. Next, a sidewall film is formed around the inversion pattern, and the periodic pattern is removed selectively. Thereafter, the processing object is etched using the sidewall pattern formed of the sidewall film and the non-periodic pattern surrounded by the sidewall film as masks.

Pattern forming method

A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a plurality of first buried wirings and a plurality of second buried wirings located in the insulating film at predetermined intervals alternately in a direction parallel to a surface of the semiconductor substrate. Each second buried wiring is formed so that a width between both side surfaces thereof is increased from a lower end toward an upper portion and at an upper surface the width is larger than a width at an upper surface of each first buried wiring.

Method of fabricating semiconductor device and the semiconductor device

A method of manufacturing a non-volatile semiconductor memory device of an embodiment includes: forming, on a semiconductor substrate, an element isolation region to be filled with a first insulating film; forming memory cell gate electrodes on element regions; etching the first insulating film so that the first insulating film remains in the element isolation region of a region in which a select gate electrode is to be formed; forming a second insulating film on the memory cell gate electrodes so that an air gap is created between the memory cell gate electrodes; forming two select gate electrodes; forming carbon side walls on the select gate electrodes; implanting ions of an impurity between the two select gate electrodes with the side walls as a mask; and removing the carbon side walls.

Method of manufacturing non-volatile semiconductor memory device

A semiconductor device including a semiconductor substrate; an element isolation region formed in the substrate including trenches formed at a first depth and being filled with an element isolation insulating film; an element forming region formed on the substrate and being surrounded by the trenches; a gate electrode formed along a first direction on the element forming region via a gate insulating film, the gate electrode extending over the element insulating film filled the trenches extending along a second direction; a source/drain region having a second depth less than the first depth formed in the element forming region beside the gate electrode and having an exposed surface exposed to a trench sidewall; wherein the upper surface of the element isolation insulating film exclusive of a portion underlying the gate electrode is located at a third depth greater than the second depth and less than the first depth.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively. The coating-type oxide films are not buried in the second element isolation insulating trenches.

A semiconductor device includes a gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the gate insulating film, a second gate electrode formed on the gate insulating film between the first gate electrode and a contact plug, a first silicon oxide film formed above the substrate between the first and second gate electrodes, a first silicon nitride film formed along the substrate and a side surface of the second gate electrode between the contact plug and the second gate electrode, a second silicon oxide film formed on the first silicon oxide film, the first gate electrode and the second gate electrode, the second silicon oxide film including an upper surface having a height greater than the height of a first upper surface of the first gate electrode relative to the substrate, and a second silicon nitride film formed on the second silicon oxide film.

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Mie, Japan

Koichi Matsuno