Fujitsu Corporation

Fujitsu Microelectronics Limited

Fujitsu Semiconductor Limited

Koichi Kuroiwa

Shoji Taniguchi

Masami Kanasugi

Mahiro Hikita

Yoshikazu Yamada

Hideyuki Iino

Hiroyuki Fujiyama

Norihiro Ikeda

Makoto Muranushi

Kenji Shirasawa

Koichi Hatta

Takanobu Kashiwagi

Shinichi Utsunomiya

Noriko Kadomaru

Makoto Miyagawa

Hiromasa Takahashi

Seiji Suetake

Jun Iwata

Tatsuya Nagasawa

Koji Nozoe

Masaharu Kimura

Kunimitsu Itashiki

Junichi Sugimoto

Takeo Sasaki

Sumimasa Sunaga

Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data terminal and a first master and a second master coupled to the memory controller, wherein the memory controller supplies a control signal corresponding to a memory access based on the first master and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with a rising edge and a falling edge of a clock signal, respectively, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with the rising edge and the falling edge, respectively.

Semiconductor integrated circuit, memory system, memory controller and memory control method

A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source voltage not lower than a data-holding-guarantee voltage; a data check unit detecting error in the data held by the first memory based on the check code; and reloading units copying only the data corresponded to the block having a data error detected therein by the data check unit, from the storage device to the first memory, to make it possible to detect any error in the data held in the first memory to thereby guarantee the data, and to lower the source voltage to be supplied to the first memory.

Semiconductor device

A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for turning on/off power corresponding to row addresses of the memory cell array, an address control section for exercising sequence control on the basis of a write pointer (WP) generated at the time of a write signal being inputted for designating a row address to which data of a predetermined data stream is to be written and a read pointer (RP) generated at the time of a read signal being inputted for designating a row address from which the data is to be read out, and a switch signal output section for generating switch signals for controlling the switch on the basis of the WP and the RP.

Semiconductor memory and electronic device

Shift code patterns at four continuous phases obtained by dividing 15 shift code patterns given to the respective flip-flops of a linear feedback shift register of degree 4 into four parts are stored in a code memory (). Besides, mask code patterns to shift a phase of a PN code (PN) to be generated by every four phases, are stored in a code mask memory (). Next, a logical operation is performed at a phase shift circuit () by using the shift code pattern outputted from the code memory () and the mask code pattern outputted from the code mask memory (), to generate a PN code (PN) having a code length of 15 from a random phase.

PN code generator, GOLD code generator, PN code despreader, method for generating PN code, method for generating GOLD code, method for despreading PN code and computer program

A processor () having an instruction memory () supplies addressing information and setting values to be set to registers (REGA to REGD) to a setting interface unit (), and address values of the registers are outputted from an address output unit () based on the addressing information. The outputted address values and the setting values are outputted respectively to registers to set setting values, so that the processor can set the setting values to be set to the registers without being conscious of the addresses of the registers, and thus it becomes possible to reduce addressing portions of the respective registers in the instruction codes, and reduce the number of instruction codes, which facilitates coding of the instruction codes.

Initializing function block registers using value supplying setting interface coupled to table linking block identifier to multiple register address set

The present invention provides a synchronization establishing device and method for establishing synchronization at a high speed in a receiver. This synchronization establishing device includes a storage unit that accumulates reception data, and a matched filter that reads out the reception data accumulated in the storage unit in parallel and determines a correlation value by obtaining correlation between a common code and the reception data in parallel.

Synchronization establishing device, method of establishing synchronization, and receiver

A power threshold value () is set to be compared with a correlation power value detected by a correlator () and a power conversion section (). As a result of comparison by a comparator (), only the correlation power values that exceed the threshold value () are stored in a power value memory (), and unnecessary correlation values at noise levels are not stored in the memory () so that the number of power values stored can be decreased. With this construction, the necessary memory capacity can be decreased, and the process of searching for the maximum value from the correlation power values stored in the memory () can be performed at a higher speed.

Cell search method, communication synchronization apparatus, portable terminal apparatus, and recording medium

When changing the number of oversamples is performed, tap factors selected by selectors, which respectively correspond to holding parts in a shift register, are changed back to a predetermined number of tap factors used before the changing of the number of oversamples, in which every time input data is accepted, the changes of the tap factors are performed in sequence, starting from the selector corresponding to the holding part at the input side. This allows the individual selectors to select proper tap factors according to the input data after the changing of the number of oversamples. As a result, the continuity of the output data is maintained even before and after the number of oversamples is changed.

Oversampling FIR filter, method for controlling the same, semiconductor integrated circuit having the same, and communication system for transmitting data filtered by the same

A receiving unit for receiving a CDMA system signal having a plurality of multipath components is intended to reduce the size. A receiving section receives a CDMA system signal. A storage section stores the signal received by the receiving section. A demodulation section demodulates each of multipath components included in the received signal stored in the storage section with a despreading code. A control section controls for demodulating a plurality of the multipath components by causing the demodulation section to perform a time division multiplex process. A Rake combining section performs the maximal ratio combining of output from the demodulation section to generate a demodulated signal.

Receiving unit and semiconductor device

An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.

Error detector, semiconductor device, and error detection method

The FIR filter separately receives input data consisting of transmitting information and composed of bit strings, and additional data which is added in order to transmit the input data. The input data is operated with the additional data. A difference between the additional data corresponding to previous data (for instance, most recent data) among the input data and the additional data corresponding present data is obtained, and the difference and the previous data are operated. Then, the operation results are added and the resultant is outputted as a filter response. The input data and the additional data are separately received to be operated so that the circuit scale of the filter is reduced. Therefore, a chip of the semiconductor integrated circuit can be downsized and thereby cost reduction in the communication system can be realized.

FIR filter, method of operating the same, semiconductor integrated circuit including FIR filter, and communication system for transmitting data filtered by FIR filter

A semiconductor device in which consumption of power attendant on a leakage current in a block where the power is turned on and off intermittently is reduced. In the semiconductor device according to the present invention, an error check necessity judgment circuit judges on notification from an error check necessity notification circuit located in a block where the power is not disconnected whether an error check must be made, and an error check execution circuit makes an error check on data loaded from an external memory at the time of a boot in accordance with the judgment of the error check necessity judgment circuit. An error check cannot completely be omitted. Therefore, to ensure the reliability of a system, an error check is forcedly made once whenever a boot is performed times set by an error check interval setting circuit. This shortens intermittent operation time by time taken to make an error check, resulting in a reduction in consumption of power attendant on a useless leakage current.

Device and method for checking boot error in intermittent receiving operation

A receiving unit, receiving method, and semiconductor device that reduce the size of circuits in a receiving unit. A receiving section receives signals sent from a base station and transmitted through a plurality of paths. A path tracking section detects timing of each of the plurality of paths through which the signals received by the receiving section were transmitted. A demodulating section demodulates the received signals by performing a despreading process according to the timing of the plurality of paths detected by the path tracking section. A correlation value calculating section calculates a correlation value between the received signals and a spreading code. A destination selecting section provides output from the correlation value calculating section to the path tracking section in the case of performing a path tracking process by the path tracking section and provides output from the correlation value calculating section to the demodulating section in the case of demodulating the received signals by the demodulating section.

Receiving unit, receiving method and semiconductor device

A semiconductor device that quickly saves data stored in an area to which power is supplied intermittently. Power is supplied intermittently to a first area. Power is supplied continuously to a second area. A memory is located in the second area. A save circuit saves data used in the first area in the memory before the supply of power being stopped. A restoration circuit restores data which has been saved in the memory to a predetermined circuit in the first area. A power supply control circuit supplies power to the memory if data has been saved in the memory. Otherwise the power supply control circuit stops the supply of power to the memory.

Memory device including backup memory for saving data in standby mode

There are provided an arithmetic unit and a receiver unit which execute an arithmetic operation at a high speed and allow reduction of the size thereof. An input section inputs data of the data group. First to n-th (n&#x3e;1) storage sections have a capacity capable of storing at least part or all of the data group. A readout section selects one of the first to n-th storage sections and reads out therefrom a data group already stored therein. An arithmetic section performs a predetermined arithmetic operation between the data group read out by the readout section and the data group newly inputted by the input section. A writing section writes a result of the predetermined arithmetic operation by the arithmetic section in a predetermined one of the storage sections, which is not selected by the reading section as the one from which the data group already stored therein is to be read out.

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Kawasaki, Japan

Koichi Kuroiwa