Disco Corporation

Azbil Corporation

Koichi Kondo

Kazuma Sekiya

Akihito Kawai

Keiichi Kajiyama

Yasuomi Kaneuchi

Tetsuya Shimakata

A manufacturing method for a stacked wafer configured by bonding a mother wafer having a plurality of first semiconductor device and a stacking wafer having a plurality of second semiconductor devices. The manufacturing method includes the steps of attaching a protective member to the front side of the stacking wafer to protect the second semiconductor devices, next grinding the back side of the stacking wafer, next bonding the front side of a reinforcing wafer through a bonding layer to the back side of the stacking wafer, next dividing the stacking wafer together with the reinforcing wafer into the plural second semiconductor devices, next bonding the front side of each second semiconductor device to the front side of the mother wafer to thereby connect the electrodes of each second semiconductor device to the electrodes of the corresponding first semiconductor device of the mother wafer, and finally grinding the reinforcing wafer bonded to the back side of each second semiconductor device to thereby remove the reinforcing wafer.

Stacked wafer manufacturing method

When the damping time constant D&#x3c4; is changed to D&#x3c4;=0, the sampling period Ts is automatically changed from 100 ms to 50 ms. The sampling time is automatically changed from 60 ms to 30 ms. Thus, when the damping time constant D&#x3c4; is changed to D&#x3c4;=0, a processing unit samples an electrical signal corresponding to the pressure difference of a fluid detected by a differential pressure sensor for the sampling time ts=30 ms in every sampling period Ts=50 ms, and finds the measurement value &#x394;P of the differential pressure by performing a variety of operation processing including a linearization operation and a square root operation on the sampled electrical signal. In the operation processing, the processing unit does not perform a damping operation.

Differential pressure transmitter

A processing method for a package substrate having a base substrate partitioned by a plurality of crossing division lines to form a plurality of chip forming areas where a plurality of semiconductor chips are respectively formed and molded with resin. The package substrate has a resin surface and an electrode surface opposite to the resin surface. The processing method includes a warp correcting step of cutting the package substrate from the resin surface or the electrode surface along the division lines by using a cutting blade to form a cut groove, thereby correcting a warp of the package substrate, and a grinding step of grinding the resin surface of the package substrate in the condition where the electrode surface of the package substrate is held on a holding table after performing the warp correcting step, thereby reducing the thickness of the package substrate to a predetermined thickness.

Processing method for package substrate

An underfill material is provided on the surface of a wafer in such a manner as to cover bumps, then the wafer is irradiated with a laser beam from the surface thereof and along planned cutting lines so as to remove an insulation layer and the underfill material present over the planned cutting lines, and the debris generated in this instance are deposited on the underfill material and are thereby prevented from being deposited on the wafer surface and/or on the bumps. Subsequently, a surface layer of the underfill material is cut so as to make the bumps flush in height and to expose the tips of the bumps.

Method of processing wafer

A method of processing a wafer having a device area where a plurality of devices are formed on the front surface and an extra area surrounding the device area and comprising electrodes which are formed in the device area, comprising: a reinforcement forming step for removing an area, which corresponds to the device area, in the back surface of the wafer to reduce the thickness of the device area to a predetermined value and keeping an area, which corresponds to the extra area, in the back surface of the wafer to form an annular reinforcement; and a via-hole forming step for forming a via-hole in the electrodes of the wafer which has been subjected to the reinforcement forming step.

Growing community of inventors

Ota-ku, Japan

Koichi Kondo