Oki Electric Industry Co., Ltd.

Koichi Kihara

Yuzuru Masuya

Takashi Ishiguro

Junji Arai

Kenichi Uchino

Koichi Yamazaki

Takeshi Shimomura

Yasuhiro Tazoi

Yorihisa Takeuchi

Jiro Asoh

An echo canceler has an adaptive filter that generates an echo replica signal from a far-end signal. The filter coefficients of the adaptive filter are updated according to a residual error signal, which is obtained by subtracting the echo replica signal from a near-end signal to cancel echo. A background noise estimator estimates the near-end background noise power level from the residual error signal. A step size calculator uses the estimated near-end background noise power in determining the step size of the adaptive updating of the filter coefficients. When the estimated near-end background noise level is high, a small step size is used, which improves echo cancellation under these conditions. When the estimated near-end background noise level is low, a larger step size is used to permit rapid convergence of the filter coefficients.

Echo canceler and echo canceling method

A redundancy gateway system that can avoid short interruption of data communication caused by system switching in gateway units configured in a multiplex manner for a plurality of systems, and that can maintain the communication state prior to the system switching and avoid degradation of communication quality. A duplicate of a received packet is generated, thereby supplying the packet of the same content to a configuration of gateway units. For each packet, a common write pointer corresponding to identification information appended to the packet is generated. Each gateway unit writes the packet to its own jitter buffer in accordance with the common write pointer corresponding to each supplied packet, sequentially reads out the written packet from the jitter buffer, and generates a TDM signal. One of the gateway units is selectively switched and only the TDM signal generated by the one gateway unit is supplied to a TDM network.

Redundancy gateway system

A bridge device for connecting networks together via data link layers, that assigns input port numbers unique to each port, to headers of input memory access control packets. A content-addressable memory stores destination addresses and groups of port numbers corresponding to the destination addresses. A determiner such as a controller determines whether or not a destination address of a memory access control packet is stored in the memory and determines whether or not a port number corresponding to the destination address coincides with an input port number of the memory access control packet. Based on the determinations made by the determiner, a selector selects one of the following as an output port number: either a port number corresponding to the destination address, or a port number designating all ports other than the input port, or a port number not designating any ports. An output port number assigner assigns an output port number to a memory access control port. Output filters such as gate circuits sequentially receive memory access control packets output by the assigner, and determine whether or not the output port numbers assigned to the headers of the packets are numbers of the ports to which the filters are themselves connected and allow passage of only those packets with the self-designating output port numbers, which are therefore actually addressed to their own output port.

Network bridge using only hardware to process media access control (MAC)

Growing community of inventors

Chiba, Japan

Koichi Kihara