Kabushiki Kaisha Toshiba

Micron Technology Incorporated

Intel Corporation

Sandisk Corporation

Toshiba Memory Corporation

Kioxia Corporation

Nippon Kokan Kabushiki Kaisha

Koichi Kawai

Kenichi Imamiya

Hiroshi Nakamura

Koji Hosono

Toshio Yamamura

Tomoharu Tanaka

Akira Goda

Krishna Kumar Parat

Yoshihiko Kamata

Khandker N Quader

Kazushige Kanda

Ken Takeuchi

Takuya Futatsuyama

Pranav Kalavade

Toru Tanzawa

Yoshiaki Fukuzumi

Noboru Shibata

Koji Sakui

Peter Sean Feeley

Hitoshi Shiga

Sundararajan Sankaranarayanan

Satoru Tamada

Yasushi Kameda

Michael M Abraham

Tamotsu Murakoshi

Mikito Nakabayashi

Tetsuji Manabe

Eric Nien-Heng Lee

Yuichi Einaga

Chang Hua Siau

Jeremy Binfet

Takehiro Hasegawa

Giuseppina Puzzilli

Masatsugu Kojima

Raj K Bansal

Tejas Krishnamohan

Tyson M Stichka

Brian J Soderling

Arnaud A Furnemont

Minoru Mikuriya

Memories might include a controller configured to cause the memory to apply a first voltage level indicative of a data state of a memory cell of an array of memory cells to a control gate of a transistor, retain the first voltage level on the control gate of the transistor, connect a first source/drain of the transistor to a data line corresponding to the memory cell while applying a second voltage level to a second source/drain of the transistor and while retaining the first voltage level on the control gate of the transistor, and apply a programming pulse to a control gate of the memory cell while the data line is connected to the first source/drain of the transistor.

Memory for programming data states of memory cells

A memory device includes a sense amplifier (SA) latch coupled to a sense node. A dynamic latch (DL) is connected to the SA latch and coupled to sense node. A sense line includes the sense node and is selectively connected to the SA latch, the DL, and a bit line that is coupled to a memory cell string. Control logic is coupled to the SA latch and the DL, and to: cause a pre-program verify voltage to boost the sense node; and, in response to detecting a high bit value stored in SA latch, cause a voltage to turn on set transistor(s) of DL so that a first bias voltage or a second bias voltage is stored at a latch transistor. The first bias voltage is useable for slow programming of a selected memory cell and the second bias voltage is useable for fast programming of the selected memory cell.

Memory devices using a dynamic latch to provide multiple bias voltages

Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

Semiconductor devices including stacked dies with interleaved wire bonds and associated systems and methods

A device includes an array of memory cells with a first word line coupled to at least a subset of the array of memory cells and control logic coupled to the first word line. The control logic to detect, within a queue, a first read command to read first data from a first page of the subset and a second read command to read second data from a second page of the subset. The control logic is further to cause a voltage applied to the first word line to move to a target value. The control logic is further to cause a page buffer to sense the first data from a first bit line coupled to the first page and to sense the second data from a second bit line coupled to the second page. The control logic is further to cause the first word line to be discharged.

Read-time overhead and power optimizations with command queues in memory device

A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.

Memory devices including multiplexer devices, and related electronic systems

A device includes an array of memory cells having a word line coupled to at least a subset of the array, a queue, and control logic. The control logic: detects a first read command to read first data from a first page of the subset; accesses a second read command in the queue, the second read command to read second data from a second page of the subset; causes a voltage applied to the word line to ramp up to an initial value; causes the voltage to move to a target value; directs a page buffer to sense the first data from a first bit line coupled to the first page of the subset; directs the page buffer to sense the second data from a second bit line coupled to the second page of the subset; and causes the word line to be discharged.

Microelectronic devices, and related memory devices and electronic systems

In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Semiconductor integrated circuit adapted to output pass/fail results of internal operations

Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

Erase and soft program for vertical NAND flash

In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory array, the storage device to program, during a first programming pass, a plurality of cells of a first wordline of the NAND flash memory array to store a first page of data; initiate a read of the first page of data prior to completion of loading of a second page of data to be programmed during a second programming pass; and program, during the second programming pass, the plurality of cells of the first wordline of the NAND flash memory array to store the first page of data and the second page of data.

Method and apparatus for initiating pre-read operation before completion of data load operation

Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

Partial page memory operations

Growing community of inventors

Yokohama, Japan

Koichi Kawai