Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Koichi Kanzaki

Minoru Taguchi

Shigeru Atsumi

Sumio Tanaka

Akihiko Furukawa

Shuichi Kameyama

Yoshitaka Sasaki

Gen Sasaki

Hidemitsu Ogura

Kenji Shibata

A non-volatile semiconductor device comprises a memory cell having a P-type silicon substrate, an N-type diffusion region formed in the substrate and serving as a word line, N-type diffusion region one serving as a source and the other as a drain of the cell transistor, a floating gate extending from a region above the diffusion region over a region above between diffusion regions, and a bit line connected to the diffusion regions. Such a memory cell is characterized in that a passivation film is formed on an interlayer insulation film insulating the floating gate and the bit lines from each other, and that a contaminant shut-off layer is provided between the passivation film and the floating gate. With this structure, the route carrying contaminants into the cell can be shut off even during manufacture thereof, achieving a high reliability of the product.

Non-volatile semiconductor memory device with contamination protection

A second impurity diffusion layer is formed in a semiconductor substrate at a fixed distance from a first diffusion layer in the substrate. The diffusion layer is supplied with a program potential. An electrode is placed on the channel region between the first and second diffusion layers. Non-selected memory cells are prevented from becoming half-selected by electrically separating the first diffusion layer from the program potential according to signals from the electrode, resulting in substantial improvements in the reliability of the semiconductor device.

Nonvolatile semiconductor memory device

A semiconductor device wherein collector connecting wiring made of for example n.sup.+ -type polycrystalline silicon layer is formed by an anisotropic etching which simultaneously engrave a groove in a semiconductor substrate. A collector layer is formed on a non-etched projection, while base contact hole is formed in the lower portion of the groove. Therefore, the base contact hole is not contacted with collector layer, thus preventing the flow of a leakage current and short-circuiting therebetween.

Semiconductor device and method for manufacturing the same

A method of manufacturing a semiconductor device wherein grooves are formed between vertical type-npn transistors and insulating oxide layers are formed on the bottoms of the grooves, thereby preventing parasitic p-n junctions, which is characterized in that said grooves are formed by using as a mask a conductive pattern containing an impurity for forming an impurity region or by using as a mask an insulating film formed by the annealing of the conductive pattern.

Method for manufacturing semiconductor device utilizing selective

A method for manufacturing a semiconductor integrated circuit includes diffusing an impurity of a second conductivity type into polycrystalline silicon layers formed on a first conductivity region in a substrate to form second conductivity regions, the polycrystalline silicon layers constituting first electrode wirings to the second conductivity regions; forming a thick oxidation film on the polycrystalline silicon layers and a thin oxidation film on the exposed surface of the substrate by a heat oxidation treatment; and removing the thin oxidation film to form a second electrode wiring to the first conductivity region, said second electrode wiring being insulated from the polycrystalline silicon layers by the thick oxidation film. The method provides integrated circuits such as I.sup.2 L circuits which are capable of high speed operation and a high packaging density.

Method for manufacturing a semiconductor integrated circuit utilizing

An integrated circuit device is provided in which an I.sup.2 L element and linear transistor are formed on a single chip such that they coexist. In this device, the base and collector regions of a vertical transistor of the I.sup.2 L element are formed such that they are deeper than the base and emitter regions of the linear transistor.

Method of fabricating an I.sup.2 L element and a linear transistor on

An oxide layer is partially formed on an n-type region surrounded by a field oxide region. A base region of a switching transistor is formed in the n-type region using as a mask the oxide layer. Arsenic-doped polysilicon layers are selectively formed simultaneously on the surfaces of the oxide layer and the base region. Using the polysilicon layers as a mask, the emitter and collector regions of an injector transistor and the external base region of a switching transistor are formed in the n-type region and the base region respectively. Arsenic doped into the polysilicon layers is diffused into the base region, so that the collector regions of the switching transistor are self-aligned with the polysilicon layers.

Growing community of inventors

Kawasaki, Japan

Koichi Kanzaki