Fujitsu Corporation

Fujitsu Microelectronics Limited

Koichi Itaya

Hitoshi Watanabe

Miki Takagi

Hiroji Takeyama

Takehiro Yamazaki

Toshihito Shimizu

Ryuji Shimizu

Hideaki Konishi

Osamu Ōkano

Kazuyuki Yamamura

Junko Kumagai

Yuko Katoh

Naoko Karasawa

Takeshi Doi

Daisuke Tsukuda

An apparatus for supporting verification includes a detecting unit that detects description data of a false path from setting data for a system mode operation of a target circuit to be verified; an analyzing unit that analyzes the description data in the system mode operation and a test mode operation of the target circuit; a diversion determining unit that determines, based on a result of analysis by the analyzing unit, whether the description data is divertible to the test mode operation; and a generating unit that generates setting data for the test mode operation based on a result of determination by the determining unit.

Method and apparatus for supporting verification, and computer product

A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.

Method and apparatus for supporting designing of LSI, and computer product

A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.

Circuit designing apparatus, circuit designing method and timing distribution apparatus

A logic circuit includes a combinational circuit,and a sequential circuit, outputs D,to D,of the combinational circuit,are provided to the respective data inputs D of flip-flops,to,of the sequential circuit through respective multiplexers,to,, and the flip-flops,to,are cascaded through the multiplexers,to,to construct a scan path. AND gates,to,are provided for preventing changes in outputs of the flip-flops,to,from being transmitted to the combinational circuit,when the scan mode signal *SM is active, whereby the combinational circuit,is kept inoperative when data is serially transferred on the scan path consisting of the D flip-flops,to,, an inverter,and the multiplexers,to

Semiconductor integrated circuit having scan path

Growing community of inventors

Kawasaki, Japan

Koichi Itaya