Hitachi, Ltd.

Koichi Ishii

Masamori Kashiyama

Shun Kawabe

Masami Usami

Yaoko Nakagawa

Vector registers having logically equal address are arranged as two banks which can independently access ultra high speed RAM's. One bank holds all even-numbered elements of vector data and the other bank holds all odd-numbered elements of the vector data. A write address generator and a read address generator which are one half as fast as a clock rate of a machine cycle and which have a phase difference of one half period therebetween are provided so that the clock rate of the machine cycle may be set to one half of a total time of a write pitch and a read pitch of the vector registers.

Vector processor performing data operations in one half of a total time

The vector processing apparatus fetches vector operands designated by an instruction from a storage to an operand buffer in a vector processor. The vector processor reads out and processes the elements of the vector operands stored in the operand buffer. The vector processor controls fetching of the element to be next processed from the operand buffer in accordance with the operation result. Thus, a vector operation of a type in which the increment of the indices of the vector operands depends on the operation result is carried out.

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Hadano, Japan

Koichi Ishii