Hitachi, Ltd.

Koichi Ikeda

Kenichi Kurosawa

Michio Morioka

Tetsuaki Nakamikawa

Hiroshi Iwamoto

Toshihiro Okabe

Hidetada Fukunaka

Hiroshi Ohguro

Takaaki Nishiyama

Kozi Nakamura

A highly reliable computer system is intended to duplicate processors, compare the outputs of the processors with each other and enhance the validity of the output of processor system. If a mismatch between the outputs is detected, one of the processors performs a process of saving an internal state of the processor in amain memory and diagnosing factor of the detected mismatch. If the process is recognized to be continued in a duplex mode, the processors are re-synchronized by a processor reset, and initialize themselves and restore the internal information saved in the main memory for continuing the process having been proceeded before the fault occurred.

Fault recovering system provided in highly reliable computer system

In a partial write control apparatus for a memory having a high speed operation mode such as a nibble mode or a page mode, when a partial write request for a plurality of words including those which require partial write is received, a memory control signal generator causes the memory to read successively all the words requiring partial write in a single high speed operation mode read cycle. A merging circuit merges those portions of the read-out words which need no alteration with write data and forms a group of updated complete words. Then, the memory control signal generator causes the memory to write successively these words in a single high speed operation mode write cycle.

Partial write control apparatus

In an information processing system utilizing a virtual storage, an address translation look-aside buffer for translating a logical address into a physical address is provided to access the main storage by use of the translated physical address. The processing system has a storage control unit for controlling the operation of the address translation look-aside buffer and the main storage, which are connected with a common bus through which addresses and data are transferred on a time-division basis. The storage control unit has a bus control circuit for controlling the common bus so that addresses are transferred from the translation look-aside buffer and data is transferred to the main storage on the common bus at different times.

Virtual address system having fixed common bus cycles

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Machida, Japan

Koichi Ikeda