Sanyo Electric Co., Ltd.

Koichi Hirata

Tetsuro Asano

Mikito Sakakibara

Nobuyuki Sekikawa

Shigeyuki Murai

Hidetoshi Ishihara

Wataru Andoh

Yoshibumi Nakajima

Hisaaki Tominaga

Toshikazu Hirai

Masaaki Momen

Takayoshi Higashino

Katsuaki Onoda

Noriyasu Katagiri

Masahiro Uekawa

Tsutomu Aono

Osamu Isaki

Katsuaki Onada

Mikita Sakakibara

Shinya Enomoto

A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layersuperimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness tof the gate electrodeon the second gate oxide filmsA andB is thinner than the thickness tof the prior art. Therefore, the height gap hbetween the gate electrodeand the N+type source layerand the height gap hbetween the gate electrodeand the N+type drain layerbecome smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film

Method of manufacturing insulated gate semiconductor device

In a method of manufacturing a compound semiconductor device, individual chip patterns are projected onto a (1 0 0) surface of a GaAs wafer so that the columns and rows of the chip patterns are aligned in a direction slanting by 45 degrees with respect to a [0 1 1] direction of the GaAs wafer. The wafer is diced along this slanting direction and chipping along the edges of the individual separated chips is greatly reduced.

Semiconductor device manufacturing method using mask slanting from orientation flat

In a case of a semiconductor chip having an electrode pad to be wire-bonded to a header, securing of a fixing region is difficult since the spread of an Ag paste cannot be controlled, therefore, there has existed a problem such that stable manufacturing could not be carried out. Also, there existed a problem such that realization of stable manufacturing resulted in an excessively large external package form. A projection part is provided in a header, and a fixing region of a bonding wire is secured by arranging a chip at a position shifted in a direction to become distant from the projection part. An electrode pad to be connected to the header is arranged closer to the chip center than the other electrode pads of the identical chip side, and a wire is extended therefrom to the projection part or in the vicinity thereof so as to cross the chip and is fixed. Thereby, downsizing of the package and stable manufacturing are realized.

Semiconductor device

A compound semiconductor switching device is based on a designing guideline that isolation should be assured by reducing the gate width of switching FET, thereby reducing the capacitance of the FET. Proper isolation between the two signal passes IS obtained with a FET gate width of about 700 &#x3bc;m or smaller at a signal frequency of about 2.4 GHz or higher, without employing a shunt FET.

Compound semiconductor switching device for high frequency switching

The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &#x3bc;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &#x3bc;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &#x3bc;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.

Compound semiconductor device

This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P&#x2212; type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.

Semiconductor device manufacturing method

An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.

Integrated schottky barrier diode and manufacturing method thereof

A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Manufacturing method of Schottky barrier diode

A local oscillation FET has a source connecting pad, a drain connecting pad and a gate connecting pad. The source connecting pad occupies one corner of a substrate, and the drain and gate connecting pads are placed at the neighboring corners so that the three connecting pads form an L shape on the substrate. As a modification to this configuration, another source connecting pad is placed at the remaining corner of the substrate so that the drain and gate connecting pads are shielded from each other by the two source connecting pads. These device configurations contribute to size reduction of the local oscillation FET.

A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t of the gate electrode on the second gate oxide films A and B is thinner than the thickness t of the prior art. Therefore, the height gap h between the gate electrode and the N &plus; type source layer and the height gap h between the gate electrode and the N &plus; type drain layer become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film

Insulated gate semiconductor device and its manufacturing method

A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film ( ) and the first polycrystalline silicon layer ( ) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad&bull;polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.

Semiconductor device having capacitance element and method of producing the same

Schottky barrier diode

The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.

Compound semiconductor device with depletion layer stop region

To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (,) and the first polycrystalline silicon layer (,) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad.polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.

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Ashikaga, Japan

Koichi Hirata