Mitsubishi Denki Kabushiki Kaisha

Koichi Hasegawa

Tetsuya Iga

A semiconductor integrated circuit having a plurality of power source voltages in one chip and which comprises delaying means which accurately implements a predetermined delay time into a signal. An inverter circuit block receives at its input part an output from a NAND gate. An output from the inverter circuit block is coupled to a node of a phase comparing part through a switch. The output from the inverter circuit block is also coupled through another switch to an input part of another inverter circuit block whose output is coupled to the node of the phase comparing part through still another switch. A control signal is set at a L level if the phase comparing part is to operate at a first power source voltage and set at a H level if the phase comparing part is to operate at a second power source voltage which is larger than the first power source voltage.

Semiconductor integrated delay circuit

A flip-flop circuit of ECL structure includes an ECL circuit portion and a level shift circuit portion including a circuit having a pair of resistors. The ECL circuit portion applies a differential signal to one end of each of the resistors, and Q and/Q output signals are derived from the other ends of each of the resistors. The amount of level shift down of the signals when shifted by the resistors is enabled to be set to any relatively small amount, whereby the ECL circuit is permitted to operate at a low voltage.

ECL circuit

A voltage reduction circuit is electrically inserted between between a first power supply pad and a power source voltage supplying portion of a bipolar circuit part. Receiving a control signal from a CMOS circuit part, the voltage reduction circuit reduces a power source voltage given thereto via the power supply pad, thereby producing a reduced power source voltage and outputting the reduced power source voltage to the power source voltage supplying portion of the bipolar circuit part. Hence, even though the same power source voltage is commonly supplied to the power supply pads of the bipolar circuit part and the CMOS circuit part via the same external power source pin, one of the bipolar circuit part and the CMOS circuit part receives the reduced power source voltage from the voltage reduction circuit. Thus, it is possible that a power source voltage to the CMOS circuit part and a power source voltage to the bipolar circuit part are different without increasing the number of external power source pins.

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Itami, Japan

Koichi Hasegawa