Kabushiki Kaisha Toshiba

Koichi Dewa

Fumitaka Sato

Masayo Yamaki

Makoto Sakai

Hiroyuki Oda

Toshimitsu Saito

Toru Hanada

Toshikazu Morisawa

Keiichi Uehara

Tohru Mamata

Makoto Kosaka

Shigeru Satake

Hiroyuki Tsukada

Kyoji Hayashi

Haruhiko Banno

Yasuhiro Nishino

When a PC main body wakes up, docking condition discrimination for checking if a LAN controller can be used is made. If the docking condition is satisfied, the LAN controller is set in an operative state, and the PC main body is used while being locked by a lock mechanism. When the WOL function is enabled, a signal WOLEN is activated. In this state, even when the PC main body goes to a sleep state and a signal DOCPWON is turned off, the LAN controller is kept powered. In this case, since the lock mechanism is unlocked, the user can immediately detach the PC main body from a LAN docker and can carry it to a location of his or her choice.

LAN docker unlocking system

When a user instructs acceleration or deceleration of the CPU processing speed with an &ldquo;accelerator&rdquo; button or a &ldquo;brake&rdquo; button, a speed control MMI informs power management system software of the corresponding information to change the CPU processing speed. The change is recorded on a speed management database in correspondence with the name of the application program which is currently being executed. Every time acceleration or deceleration of the CPU processing speed is instructed by the user, speed management data is formed on the speed management database. By using the speed management data, the CPU processing speed can be dynamically controlled for each piece of software when it is executed. Further disclosed is a novel power dissipation control system for a microprocessor, adapted to be used in conjunction with the above described MMI.

System and method for dynamically controlling processing speed of a computer in response to user commands

When a user instructs acceleration or deceleration of the CPU processing speed with an 'accelerator' button or a 'brake' button, a speed control MMI informs power management system software of the corresponding information to change the CPU processing speed. The change is recorded on a speed management database in correspondence with the name of the application program which is currently being executed. Every time acceleration or deceleration of the CPU processing speed is instructed by the user, speed management data is formed on the speed management database. By using the speed management data, the CPU processing speed can be dynamically controlled for each piece of software when it is executed. Further disclosed is a novel power dissipation control system for a microprocessor, adapted to be used in conjunction with the above described MMI.

System and method for dynamically controlling processing speed of a

Dedicated registers are arranged in a status LCD control gate array connected to a system bus, and the dedicated registers or register group and a keyboard controller are connected through a keyboard interface bus. The keyboard controller has two ports for communicating with a CPU. The keyboard controller transfers existing commands released to an application program or the like and transmits normal key data through the system bus. The keyboard controller transmits hot key data and transfers a command for realizing any other special function through the keyboard interface bus and the dedicated registers.

Portable computer having dedicated register group and peripheral

A flash memory used as a BIOS-ROM has a main block storing a BIOS and a boot block storing minimum programs executed in initializing the system. Upon a power-on operation, when a rewriting unit is connected to an expansion bus connector, a new boot block stored in a ROM of the rewriting unit is written in the flash memory. Upon the power-on operation, a key depression detecting routine in the boot block is executed to check whether a predetermined key is depressed. If the predetermined key is determined to be depressed, a rewriting program in a floppy disk is loaded in the system and executed, thereby rewriting the content of the main block into the BIOS file stored in the floppy disk.

Computer system having BIOS (basic input/output system)-ROM (Read Only

A computer has a conversion module for converting a password to be registered into a compressed-bit row in accordance with a predetermined rule. A registration module stores the compressed bit row of the registered password in a backup RAM. A conversion module converts a password to be compared with the registered password into a compressed bit row. A comparison module compares the compressed bit row of the compared password with the compressed bit row of the registered password. Upon detecting a coincidence between the two compressed bit rows, a system activation module is activated to set the system to a access allowable state.

Computer with password processing function and password processing

The selection of a keyboard on a computer system can automatically be achieved. If any externally provided keyboard which transmits transmission data upon the turning on of a computer system is connected to an external keyboard controller, a selection circuit selects that external keyboard controller for controlling the externally provided keyboard. If, on the other hand, no externally provided keyboard is connected to the external keyboard controller, the selection circuit selects an incorporated keyboard controller for controlling an incorporated keyboard which is incorporated in the computer system. When the externally provided keyboard is connected to the external keyboard controller, the selection of a keyboard by the selection circuit is achieved depending upon whether or not the computer system receives transmission data from the externally provided keyboard.

Method and apparatus for selecting a keyboard on a computer system

A basic input and output system program, (BIOS) includes a 16-bit interface hard disk controller, (HDC) control routine and an 8-bit interface HDC control routine, and also includes an automatic HDC type determination routine. The 16-bit interface HDC has an inherent I/O address (I/O port), but the 8-bit interface HDC has no inherent I/O address (I/O port). By utilizing this fact, a CPU writes specified data at the I/O address inherent to the 16-bit interface HDC. The CPU then reads out the data from the I/O address, and compares the read data with the written data. If a coincidence is obtained, the CPU determines that the 16-bit interface HDC is used, and sets up a 16-bit interface HDC control routine. On the other hand, if no coincidence is obtained, the CPU determines that the 8-bit interface HDC is used, and sets up an 8-bit interface HDC control routine.

I/O control system for a plurality of peripheral devices

When a FORMAT COMMAND is executed, a track density data indicating a track density of 96 TPI or 48 TPI is written into a discrimination area of a disk. When the disk is set into the FDD and is used, a CPU reads out track density data from the disk and produces a flag byte data, including the track density data, and stores it into a main memory. When SEEK COMMAND is executed, a track density of the disk is checked to see if it is 96 TPI or 48 TPI on the basis of the flag byte data. If it is determined that the disk of 48 TPI is set into the FDD for use in driving a disk of 96 TPI according to this discrimination, an FDC outputs a STEP signal for allowing the traveling distance of the head to be doubled as compared to an ordinary distance, thereby controlling the seeking operation by the FDD so as to assuredly move the head to a predetermined desired track.

Growing community of inventors

Tokyo, Japan

Koichi Dewa