Renesas Electronics Corporation

Arai Machinery Corporation

Arai Corporation

Other

Hitachi Medical Corporation

Hitachi, Ltd.

Hitachi Global Storage Technologies Netherlands B.v.

Renesas Electrics Corporation

Koichi Arai

Kenichi Hisada

Yasuaki Kagotoshi

Natsuki Yokoyama

Haruka Shimizu

Nobuo Machida

Hironobu Miyamoto

Koichi Yamazaki

Tatsuhiro Seki

Hisashi Toyoda

Masaki Hama

Yasunori Yamashita

Yoshiaki Sato

Terumi Takashi

Yoshiju Watanabe

Takeshi Yatsuo

Yuzo Nakagawa

Toshio Kakihara

First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

Manufacturing method of semiconductor device and semiconductor device

A shearing blade is used in a filtration device including a filtering element having a filtering surface and a plurality of filter pores provided on the filtering surface for filtering unfiltered fluid introduced into a primary side, a scraper abutting the filtering element for cleaning the filtering surface by rotating in a rotational direction, a pillar provided in the primary side to which the scraper is attached, and a tube body. The front end portion of the shearing blade is at least disposed between the filtering surface and a circle defined by the outer circumferential end of the pillar in the radial direction, and the distance between the front end portion and the filtering surface in the radial direction is shorter than the distance between the rear end portion of the shearing blade and the filtering surface in the radial direction.

Shearing member and filtration device

A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off MOSFET having a second gate electrode, a second source electrode and a second drain electrode, and a voltage applying unit which applies a voltage to the first gate electrode. The first source electrode of the junction FET is electrically connected to the second drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series, and the voltage applying unit applies a second voltage with a polarity opposite to that of a first voltage applied to the first gate electrode when the junction FET is brought into an off-state, to the first gate electrode when the MOSFET is in an on-state.

Semiconductor device

A Q value of the RF irradiation coil is easily obtained in a state in which an object is disposed in an MRI apparatus, and an SAR is predicted with high accuracy. For this, an irradiation coilirradiates an objectwith a high frequency magnetic field pulse in a state in which the objectis disposed in an imaging space, and a transmitted voltage and a reflected voltage of the irradiation coilare detected. A Q value of the irradiation coil in a state of the objectbeing disposed is obtained on the basis of the transmitted voltage and the reflected voltage. A specific absorption rate (SAR) in a case of executing an imaging pulse sequence on the object is predicted by using the Q value.

Magnetic resonance imaging apparatus and SAR prediction method

A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.

Manufacturing method for semiconductor device having an oxidation-resistant insulating film in a termination region

In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of apart of the gate insulating film part formed on/over a side face of the trench.

Semiconductor device for power transistor

In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of a part of the gate insulating film part formed on/over a side face of the trench.

In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a ptype body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p-type body layer, and the n-type drift layer between the p-type body layer and the n-type drift layer. By those measures, it is possible to inhibit the operating characteristic from varying.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a normally-on junction FET having a gate electrode, a source electrode and a drain electrode and a normally-off MOSFET having a gate electrode, a source electrode and a drain electrode. The source electrode of the junction FET is electrically connected to the drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series. The gate electrode of the junction FET is electrically connected to the gate electrode of the MOSFET.

In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.

Vertical-channel type junction SiC power FET and method of manufacturing same

The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Normally-off power JFET and manufacturing method thereof

An on-resistance of a junction FET is reduced. In a semiconductor device in an embodiment, a gate region of the junction field effect transistor includes a low concentration gate region and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, and the high concentration gate region is included in the low concentration gate region.

Semiconductor device including junction field effect transistor and method of manufacturing the same

To provide a semiconductor device having a vertical JFET excellent in off-state performance without reducing a production yield. A gate region quadrangular in the cross-section along a channel width direction is formed below a source region by impurity ion implantation. By first etching, the source region over the upper surface of the gate region is removed to separate therebetween. Then, the upper surface of the gate region is processed by second etching having an etching rate lower at the side surface than at the center of the gate region. The resulting gate region has a lower surface parallel to the substrate surface and an upper surface below a boundary between the source region and the channel formation region and having, in the cross-section along the channel width direction, a downward slope from the side surface to the center. As a result, a channel length with reduced variations can be obtained.

Growing community of inventors

Kanagawa, Japan

Koichi Arai