Nec Corporation

Nec Electronics Corporation

Renesas Electronics Corporation

Koichi Ando

Shin Koyama

Mariko Makabe

Takashi Hashimoto

Tetsuya Iida

Masamichi Fujito

Tomoya Saito

Kenichiro Nakagawa

Shunji Kubo

Hideyuki Tajima

Eiji Io

Tomohiro Hamajima

Sadayuki Ohnishi

A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

Semiconductor device

The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.

Flash memory

An NMOS transistor type nonvolatile semiconductor memory has first and second N-type diffusion layers formed in a P-type silicon layer as a source and a drain; a gate electrode formed on a channel region with an insulating film interposed therebetween, the channel region being sandwiched between the first and second N-type diffusion layers; and a charge storage layer formed in the insulating film. A direction from the first N-type diffusion layer to the second N-type diffusion layer is the same as a crystal orientation &#x3c;100&#x3e; of the P-type silicon layer. At the time of rewriting, the hot holes go over a potential barrier of the insulating film to be injected into the charge storage layer.

Nonvolatile semiconductor memory having suitable crystal orientation

A non-volatile semiconductor memory device includes a substrate, a first insulating film formed on the substrate, a second insulating film formed on the first insulating film, a plurality of granular dots formed in the second insulating film adjacent to the first insulating film as a floating gate, and a control gate formed on the second insulating film. The second insulating film is a high dielectric constant film made of oxide whose dielectric constant is higher than that of the first insulating film and whose heat of formation is higher than that of silicon oxide.

Non-volatile semiconductor memory device

A metal oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end portion located on each side of the central portion, the end portion being thicker than the central portion and formed of an oxide insulating film. The MOS transistor also includes a p-type gate electrode formed on the gate insulating film, sidewalls formed on both sides of the gate insulating film and the gate electrode, a pair of p-type source/drain areas formed in surface portions of the silicon substrate, and a channel area located between the pair of source/drain areas.

High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions

A Metal Oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end portion located on each side of the central portion, the end portion being thicker than the central portion and formed of an oxide insulating film. The MOS transistor also includes a p-type gate electrode formed on the gate insulating film, sidewalls formed on both sides of the gate insulating film and the gate electrode, a pair of p-type source/drain areas formed in surface portions of the silicon substrate, and a channel area located between the pair of source/drain areas.

Semiconductor apparatus including CMOS circuits and method for fabricating the same

Field effect transistors of an integrated circuit are fabricated on a silicon substrate, and require gate insulating layers appropriate for the purpose of individual component circuits, the active areas assigned the field effect transistors are sequentially exposed to source gas varied in the ratio between oxygen and nitrogen for growing silicon oxide and/or silicon oxynitride thereon, and the nitrogen serves as a diffusion inhibitor against the oxygen so as to form the gate insulating layers different in thickness of the order of several angstroms.

Semiconductor device having gate insulating layers different in thickness and material and process for fabrication thereof

A method for fabricating a very thin oxide film, such as a gate oxide film of a MOS transistor, by oxidizing a substrate, which method can accurately and easily control the thickness of the oxide film to a desired value. The method comprises controlling thickness of the oxide film to be formed, by adjusting partial pressure of oxygen in an ambient including oxygen, without changing temperature of oxidation of said substrate and time of oxidation of said substrate. Alternatively, the method comprises controlling thickness of the oxide film to be formed, by adjusting only pressure of an oxidizing ambient, without changing temperature of oxidation of said substrate and time of oxidation of said substrate.

Method for fabricating oxide film

A stacked storage capacitor of a dynamic random access memory cell has a p-type polysilicon layer forming an upper part of an accumulating electrode, a dielectric film structure and a p-type polysilicon counter electrode, and boron difluoride is ion implanted into a non-doped polysilicon layer for the counter electrode so as to decrease leakage current density rather than a boron-implanted polysilicon counter electrode.

Process of fabricating semiconductor device having capacitor electrode

A method of manufacturing a semiconductor device includes the step of forming a capacitor. The step includes the step of forming a lower electrode constituted by a polysilicon film which selectively covers a surface of a predetermined insulating film on a semiconductor substrate, and the step of performing heating in an atmosphere containing an SiH.sub.4 gas and removal of a native oxide film on a surface of the lower electrode, and then performing formation of a silicon nitride film without being exposed to an oxygen atmosphere.

Method of manufacturing semiconductor device

A storage capacitor incorporate in a semiconductor dynamic random access memory cell has an accumulating electrode of p-type polysilicon electricaly conencted to an n-type drain region of an associated switching transistor, a dielectric film structure covering the accumulating electrode and a counter electrode opposed through the dielectric film structure and formed of a p-type polysilicon, and the dielectric film structure is thinner than a critical thickness for a direct tunneling current by virtue of the wide potential barrier between the dielectric film structure and the p-type polysilicon and the Fermi level of the p-type polysilicon falling into the forbidden band of the other p-type polyslicon.

Semiconductor dynamic random access memory cell free from leakage

A semiconductor device has a capacitor insulating film composed of a first and a second silicon nitride film. The surface of a lower electrode of impurity-doped polysilicon is transformed into the first silicon nitride film by thermal nitriding, and thereafter the second silicon nitride film is formed by chemical vapor deposition. An upper electrode is formed on the second silicon nitride film. A silicon oxide film may be formed on the second silicon nitride film by thermal oxidation. The capacitor insulating film which has a thickness of 5 nm or less in equivalent thickness of an oxide film reduces a leakage current and improves a long-term product reliability.

Semiconductor device with capacitor insulating film and method for

A logic circuit has a logic circuit portion which includes a first MOS transistor circuit, a second MOS transistor circuit and a third MOS transistor circuit for conducting a logical operation. The logic circuit also has a first and a second bipolar transistor for driving a next stage logic circuit and an N-channel MOS transistor for discharging the charge in the base of the second bipolar transistor. There is provided an inverter circuit whose input terminal is connected either to the output terminal or the base of the first bipolar transistor. An input to the gate of the N-channel MOS transistor is supplied from the output terminal of the inverter circuit so that, when the output changes from its high level to its low level, there is no possiblity for the first and second bipolar transistors to turn to their ON-state at the same time. Consequently, all of the current which is to be supplied from the third MOS transistor circuit to the base of the second bipolar transistor flows thereto without by-passing and, as a result, there is no reduction in the collector current of the second bipolar transistor. Thus, it is possible to have the load capacitance at the next stage discharged at a high speed and hence to have the circuit operate at a high speed.

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Tokyo, Japan

Koichi Ando