Fujitsu Corporation

Fujistu Limited

Kohtaroh Gotoh

Hirotaka Tamura

Junji Ogawa

Shigetoshi Wakayama

Miyoshi Saito

Tsz-Shing Cheung

Hisakatsu Araki

Hideki Takauchi

Hisakatsu Yamaguchi

Hideki Ishida

Akira Yoshida

Norio Fujimaki

Shigeru Nishio

Takaya Chiba

Shunichiro Masaki

Takuya Saze

Koji Aoyagi

Kazuhiro Terashima

An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is &#xbd; unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.

Adaptive equalizer circuit

A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Phase interpolator for a timing signal generating circuit

Timing signal generating circuit with a master circuit and slave circuits

A multiplexer circuit, converting parallel data into serial data and synchronized with a clock signal, has a plurality of multiplexer cells that receive the parallel data. Each of the multiplexer cells has a first load, a plurality of first conductivity type transistors, and a level-changing circuit. The first conductivity type transistors are connected in series between a first power source line and a second power source line, and the level-changing circuit changes a connection node of adjacent first conductivity type transistors to a level of the first power source line.

Multiplexer circuit for converting parallel data into serial data at high speed and synchronized with a clock signal

A clock recovery circuit has a boundary detection/discrimination circuit to detect and discriminate a boundary in an input signal in accordance with a first signal. The clock recovery circuit performs clock recovery by controlling the timing of the first signal in accordance with the detected boundary, wherein boundary detection timing in the boundary detection/discrimination circuit is varied by controlling the first signal.

Clock recovery circuit and receiver circuit for improving the error rate of signal reproduction

A test circuit is incorporated in a device having an output circuit for outputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test output buffer connected in parallel with output nodes of the output circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the output nodes, and the test output buffer receives test data from the test data generating circuit and outputs the test data to the output nodes. Similarly, a test circuit is incorporated in a device having an input circuit for inputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test input buffer connected in parallel with input nodes of the input circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the input nodes, and the test input buffer receives test data from the test data generating circuit and inputs the test data to the input nodes.

Test circuit and semiconductor integrated circuit effectively carrying out verification of connection of nodes

A driver circuit transmits a signal to a receiver circuit through a signal transmission line. The driver circuit has an output driver, a front driver, and a level adjuster. The front driver drives the output driver, and the level adjuster adjusts the output level of the front driver. The output driver generates a signal whose level is variable in response to an output level of the front driver.

Timing signal generator for correctly transmitting a signal at high speed without waveform distortion

A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM

Signal transmission system having a timing adjustment circuit

Method of an apparatus for correctly transmitting signals at high speed without waveform distortion

A restoring circuit,, provided for each of the memory blocks,and,, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder,. The present row address is held in one of the registers. When amplification is started by a sense amplifier,, transfer gates,and,connected between the bit lines BL,and *BL,and the sense amplifier,are turned off to decrease the load of the sense amplifier,, the amplified signal is stored in a buffer memory cell circuit,, and accessing is completed with omitting restoring to the memory cell,. While the memory cell block,is not selected, the data held in the buffer memory cell circuit,is stored into the memory cell row addressed by the content of the selected register. The sense amplifier,has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.

Destructive read type memory circuit, restoring circuit for the same and sense amplifier

Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system

A restoring circuit,provided for each of the memory blocks,and,having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder,The present row address is held in one of the registers. When amplification is started by a sense amplifier,transfer gates,and,connected between the bit lines BL,and *BL,and the sense amplifier,are turned off to decrease the load of the sense amplifier,the amplified signal is stored in a buffer memory cell circuit,and accessing is completed with omitting restoring to the memory cell,While the memory cell block,is not selected, the data held in the buffer memory cell circuit,is stored into the memory cell row addressed by the content of the selected register. The sense amplifier,has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.

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Kawasaki, Japan

Kohtaroh Gotoh