Sharp Kabushiki Kaisha Corporation

Kohsuke Harada

Tokiyuki Okano

Sohichi Takata

Makoto Higuchi

Kenji Tanaka

Yoshiyuki Nakai

Hiroshi Tanaka

Takao Horiuchi

Yoshitaka Okahashi

Kouji Yamaji

Toru Adachi

Keiji Nakamura

An FPGA functions as an activation mode setting circuit for loading activation data stored on a PROM into a circuit setting memory and setting an activation mode when activating the CPU. The FPGA outputs an activation mode setting signal to the CPU, and the CPU is activated in the set activation mode. After the CPU is activated, it follows predetermined processing steps, and performs a control operation to load the circuit setting data stored in a storage section into the circuit setting memory. Thus, the FPGA is constructed as a circuit having a desired function, and also constructed as an activation mode setting circuit when activating the CPU.

Image processing apparatus and image forming apparatus

A storage area where compressed data is stored is divided into a plurality of divided areas having a data length of Ls. Each divided area is divided into two areas, a first area having a data length of Ld and a second area having a data length of La. A plurality of first areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed image data is composed. A plurality of second areas are gathered starting from the upper address to the lower address, whereby a memory area for compressed attribute data is composed. Compressed image data is sequentially written starting from the upper address to the lower address of the memory area for compressed image data. Compressed attribute data is sequentially written starting from the upper address to the lower address of the memory area for compressed attribute data.

Image processing apparatus, image forming apparatus, and image processing method

Reference images on the respective surfaces of a reference document transported on a transportation path are read out by a first image reading section and a second image reading section, respectively. As a result a first reference readout image and a second reference readout image are acquired. in accordance with the difference between the changes in the sub-scanning direction in the first reference readout image and the changes in the sub-scanning direction in the second reference readout image, the reading cycle of the first image reading section Xand the reading cycle of the second image reading section Xare set. This makes it possible to equalize the magnifications of the respective images on the front and back sides of the document, even if the speeds of the document at the times of passing through readout positions for the front and back sides change over time, on account of the wear of a transportation roller.

Image reading apparatus and image reading method

In an image forming apparatus, at the time of print recording of a set of image data to a plurality of recording sheets, by the use of a recording sheet interval that is an interval between a position where print recording of a recording sheet of the plurality of recording sheets ends and a position where print recording of a succeeding recording sheet starts, an image processing portion executes image processing of another set of image data read by a scanner portion and divided by an image dividing portion, in accordance with an operation command of a control portion.

Image forming apparatus

The object of the present invention is to use the same FIFO line memory for both enlargement and reduction during variable-magnification processing in the scan direction, allowing reduction in circuit board area, reduction in power consumption, and reduction in cost, and to provide an image processing apparatus that allows variable-magnification processing to be carried out such that the speed of a scanning unit that captures image data during variable-magnification processing in the cross-scan direction is constant. During processing to enlarge an image in the scan direction, image data travels from CCD circuit board, passing through gate b of selector, is written to and read from FIFO memory, and from gate b of selector is written to memory provided at variable magnification unit. At variable magnification unit, image data is read from memory a plurality of times in correspondence to enlargement ratio, changing the magnification of the image data. Furthermore, image data is output through gate a of selector to LSU unit. During processing to reduce an image, image data travels from CCD circuit board, passing through gate a of selector, is input to variable magnification unit where it is subjected to variable-magnification processing, passes through gate a of selector, is written to and read from FIFO memory, passes through gate b of selector, and is output to LSU unit.

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Nara, Japan

Kohsuke Harada