Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Kohji Yamasaki

Shuji Ikeda

Takashi Hashimoto

Toshiaki Yamanaka

Kousuke Okuyama

Yasuko Yoshida

Keiichi Yoshizumi

Kazushi Fukuda

Soichiro Hashiba

Fumiyuki Kanai

Kazuo Yoshizaki

Tsuyoshi Tabata

Kazushi Tomita

Koichi Imato

Chiemi Hashimoto

Motoko Kawashima

Junichi Takano

Mitsugu Oshima

Nobuyuki Moriwaki

Hideaki Nakamura

Shigeru Honjo

A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

Semiconductor integrated circuit device having capacitance element and

Semiconductor integrated circuit device and process of manufacturing the

Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

Semiconductor integrated circuit device having a compact arrangement of

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Akishima, Japan

Kohji Yamasaki