Fujitsu Corporation

Fujitsu Vlsi Limited

Kohji Shimbayashi

Kiyoshi Itano

Mitsuhiro Nagao

Mitsuo Higuchi

Yoshiyuki Ishida

Kiyonori Ogura

Yasuhiro Nakaoka

A semiconductor memory device is disclosed, having a plurality of memory cells, from which cell data is read out, based on at least one control signal provided to the memory device. The memory device includes a transfer gate which receives read data from one of the memory cells, a latch circuit which latches the read data sent from the transfer gate, and an output buffer which outputs data produced in accordance with the latched read data. The memory device further includes a transfer gate controller, which produces a latch control signal based on the control signal and supplies the latch control signal to the transfer gate to control an ON/OFF action of the transfer gate. A delay circuit, incorporated in the gate controller, controls level-switching timing for the latch control signal such that after switching the level of the control signal, the transfer gate is turned off with a predetermined delay.

Semiconductor memory device

A programmable logic device includes an input/output buffer, a logic array, switches for switching signal lines provided between the logic array and the input/output buffer and feedback lines between an input and an output of the logic array so as to alter the logic operation. Switching operations of the switches such as an open/close operation and a selection operation, are determined by the data stored in a plurality of non-volatile memory elements arranged in a matrix of rows and columns, the non-volatile memory elements being respectively associated with the switches. The contents of the memory elements are read out and stored in registers. The data contents of the non-volatile memory elements as thus stored in the registers are applied to control terminals of the switches.

Programmable logic device including verify circuit for macro-cell

A programmable logic device includes: a programmable AND array; an OR array operatively connected to the AND array; a plurality of external terminals; and a plurality of cell blocks operatively connected to the AND array and OR array and provided for each of the plurality of external terminals, each receiving two output signals from the OR array and outputting a signal to a corresponding external terminal based on the two output signals. By controlling an input/output of an input signal and an internally produced signal and a feedback thereof to the AND array, it is possible to realize various logic constitutions and develop a degree of freedom of the logic design in the entire device.

Programmable logic device having expanded logic capability

A programmable logic device includes an AND array; an OR array; a buffer circuit connected between the AND array and OR array; and a number of decoder arrangements operatively connected to the AND array and OR array. By constituting the buffer such that the AND array and OR array are electrically associated even in a write operation of data, namely, the buffer is brought to an enable state, a logic verify of the buffer becomes unnecessary and, accordingly, a verify/check of written data can be carried out both easily and efficiently.

Programmable logic device

A semiconductor integrated circuit device has a plurality of terminals, an internal circuit for receiving input signals from the terminals and for outputting output signals to the terminals, where the internal circuit is enabled by a chip enable signal and disabled by a chip disable signal, a non-volatile memory for storing a pin select signal which designates at least a selected one of the terminals as a chip enable control terminal for receiving a control signal which has a first logic level when instructing a power down mode of the semiconductor integrated circuit device, and a buffer part coupled to the terminals and the non-volatile memory for generating the chip enable signal and the chip disable signal responsive to the pin select signal and the control signal. The buffer part generates the chip enable signal when the control signal received by the selected one terminal has a second logic level and generates the chip disable signal when the control signal received by the selected one terminal has the first logic level to thereby set an operation mode of the semiconductor integrated circuit device to the power down mode.

Growing community of inventors

Kawasaki, Japan

Kohji Shimbayashi