Sanyo Electric Co., Ltd.

Kohji Sakata

Atsushi Wada

Seiichi Banba

Takeshi Otsuka

Hirofumi Saitoh

An analog-to-digital converter includes a track-and-hold circuit, a constant-voltage source, a threshold voltage selection circuit, a first comparator to a seventh comparator, an encoder, and a reference voltage output circuit. In a correction mode where the offsets of the first to seventh comparators are to be corrected, a track-and-hold circuit shuts off the input of an analog voltage to the first to seventh comparators by turning off the track-hold switch.

Analog-to-digital converter and threshold-value correcting method

An analog-to-digital conversion apparatus which has a variable resolution and allows a reduction in power consumption. This apparatus comprises an analog-to-digital converter (ADC) of parallel type, a controller, and an interpolation circuit. The analog-to-digital converter has a plurality of comparators connected in parallel, each for comparing potentials of an analog input signal and a reference signal. The controller generates a control signal for controlling the resolution of the analog-to-digital converter. Specifically, the controller controls the number of comparators (CMP) to operate by means of the control signal, thereby determining the resolution. The interpolation circuit interpolates the output data of the comparators that are disabled depending on the resolution. The controller avoids simultaneous operation of two adjoining comparators when the analog-to-digital converter is operated at a resolution lower than its maximum resolution.

Analog-to digital converter and analog-to digital conversion apparatus

A coincidence determining circuit determines whether first and second digital data each consisting of a plurality of bits coincide with one another. The coincidence determining circuit includes a wiring and a plurality of bit comparison circuits corresponding in number to the bits. Each bit comparison circuit includes first and second transistors connected in series between the wiring and a power supply line and third and fourth transistors connected in series between the wiring and the power supply line. The first and second transistors receive a first logical signal of an associated bit of the first digital data and an inverted signal of a second logical signal of an associated bit of the second digital data. The third and fourth transistors receive an inverted signal of the first logical signal and the second logical signal. The four transistors of each bit comparison circuit suppress an increase in circuit area.

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Gifu, Japan

Kohji Sakata