International Business Machines Corporation

Kohji Kitamura

Toshio Sunaga

Hisatada Miyatake

Hideo Asano

Kohki Noda

Hiroshi Umezaki

Hisatada Miyatke

Provided is an MRAM memory cell structure capable of preventing generation of parasitic transistors. Diodes are adopted as switching elements of an MRAM memory cell. An n-type semiconductor layer and a p-type semiconductor layer, which collectively constitute a diode, are formed on a surface semiconductor layer of an SOI substrate. The n-type semiconductor layer and the p-type semiconductor layer are disposed in a lateral direction and isolated by an isolation region, whereby the diode is isolated electrically from other elements and from the substrate.

Semiconductor device

The invention provides methods and apparatus for for determining and providing optimum write bit line current and write word line current in an MRAM. A single reference potential is used to determine the values of the write line current and the bit line current. In determining the optimal values, asteroid curves representing bit line magnetic fields Hgenerated by write bit line current Iand word line magnetic fields Hgenerated by write word line current Ifor magnetization are considered, and an asteroid curve ACis defined outside the asteroid curves of all memory cells taking manufacture variations and design margins into account. A write bit line current and a write word line current are selected such that the write current obtained by adding the write bit line current or currents and the write word line current, or the write power consumed by the bit line or lines and the write word line is minimized. Furthermore, in order to prevent multi-selection, the write bit line current and the write word line current are selected so that they generate a synthetic magnetic field on the curve between calculated points of the asteroid curve AC.

Magnetic memory and method for optimizing write current in a magnetic memory

It is one object of the present invention to provide an FPGA for which the configuration time and the time required for rewriting connection information and logic structure information can be reduced, and for which the size of the area occupied can also be reduced. In order to store connection information for an FPGA, magnetic storage elements MTJto MTJn, which are memory cells of an MRAM, are provided, and using a shift register, connection information is written to the magnetic storage elements MTJto MTJn. The shift registerincludes register elements SRto SRn, which correspond to the magnetic storage elements MTJto MTJn, to which the connection information is serially input and stored. When the power is switched on, the connection information stored in the magnetic storage elements MTJto MTJn is latched by latch elements LTto LTn, and is output to switching circuitsto interconnect logic blocks

Field programmable gate array

An object of the present invention is to provide a memory cell, a memory circuit block, a data writing method, and a data reading method which realize a reduction in the number of metal layers, cost, and the chip size and an increase of production yields and product reliability. A memory cellincluding a metal linecrossing a bit linewithout contact therewith and a second conductive structureconnecting the metal lineand a switching elementis disclosed. A write driver circuitfor driving a write current through the metal lineand a groundare connected to the metal linethrough a switchfor selecting the circuitor the ground

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Kusatsu, Japan

Kohji Kitamura