Sharp Kabushiki Kaisha Corporation

Kohji Inoue

Nobuyoshi Awaya

Keizo Sakiyama

Yukio Tamai

Yasunari Hosoi

Masayuki Fujimoto

Toshimasa Suzuki

Masayuki Tajiri

Shigeo Ohnishi

Atsushi Shimaoka

Yuji Nishi

Teruaki Morita

Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device includes: a load resistive characteristic variable circuit for each bit line connected commonly with the memory cells on the same column for selecting one of two load resistive characteristics according to a first writing operation where the resistive characteristics of the variable resistive element to be written transit from a low resistance state to a high resistance state or a second writing operation where they transit reversely; and a writing voltage pulse application circuit for applying a first voltage pulse in a first writing operation and a second voltage pulse in a second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit limes.

Nonvolatile semiconductor memory device

A semiconductor memory device comprising a memory cell array of cross-point type having memory cells each composed of a variable resistive element for storing information in the form of variation of the electrical resistance. The operating current in the programming operation is reduced. Main data lines (GDLto GDL) for supplying predetermined data line voltages to each of the corresponding data lines (DLto DL) of the memory cell arrays (BKto BK) arranged at least in the row direction extend in the row direction and are connected to the corresponding data lines (DLto DL) through individual data line selecting transistors (TDto TD) in the memory cell arrays (BKto BK). The number of data lines (DLto DL) of the memory cell arrays (BKto BK) is equal to the largest number of memory cells in which data is simultaneously programmed in one write operation.

Semiconductor memory device

A semiconductor memory device () comprises a memory cell array () in which memory cells each have a variable resistance element and the memory cells in the same row are connected to a common word line and the memory cells in the same column are connected to a common bit line, wherein during a predetermined memory action, the voltage amplitude of the voltage pulse applied to an end of at least one of the selected word line and the selected bit line is adjusted based on the position of the selected memory cell in the memory cell array () so that the effective voltage amplitude of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased falls within a certain range regardless of the position in the memory cell array ().

In a semiconductor storage device with cross point type arrays of memory cells including variable resistor elements, a selected data line and unselected data lines are supplied with a row selecting potential and a row unselecting potential through a data line selecting transistor respectively, a selected bit line and unselected bit lines are supplied with a column selecting potential and a column unselecting potential through a bit line selecting transistor respectively. Data lines and bit lines are separately driven so that when the data line selecting transistor is higher in the current driving capability than the bit line selecting transistor, a second bias voltage between the row unselecting potential and column selecting potential is lower than a first bias voltage between the row selecting potential and column unselecting potential, in the opposite case, the first bias voltage is lower than the second voltage.

Semiconductor storage device

There is provided an EPIR device which is excellent in mass productivity and high in practical utility. The EPIR device includes a lower electrode layer, a CMR thin film layer and an upper electrode layer which are laminated in this order on any of various substrates. A Pt polycrystal thin filmforming the lower electrode layer includes columnar Pt crystal grainsA,B,C, . . . and over 90% of these crystal grains is oriented to a (1 1 1) face. Columnar PCMO crystal grain groupsA,B,C, . . . are respectively locally grown epitaxially on the respective outermost surfaces of the Pt crystal grainsA,B,C, . . . . Then, the crystal faces of the crystal grains included in the PCMO crystal grain groupsA,B,C, . . . and vertical in the substrate surface normal direction are any one of (1 0 0), (1 1 0)and (1 1 1)planes.

EPIR device and semiconductor devices utilizing the same

One end of each variable resistive element, which forms a memory array, in the same row is connected to the same word line and the other end of each variable resistive element in the same column is connected to the same bit line. A first word line voltage is selected and applied to the selected word line, a second word line voltage is selected and applied to the unselected word lines, a first bit line voltage is selected and applied to the selected bit line, and a second bit line voltage is selected and applied to the unselected bit lines. The voltage difference between the first word line voltage and the first bit line voltage is set at a value that is no less than the first voltage difference that changes the resistance value of a variable resistive element, and the voltage difference between the first word line voltage and the second bit line voltage, the voltage difference between the second word line voltage and the first bit line voltage and the voltage difference between the second word line voltage and the second bit line voltage are respectively set at a value that is no greater than the second voltage difference that does not change the resistance value of a variable resistive element.

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Osaka, Japan

Kohji Inoue