International Business Machines Corporation

Samsung Electronics Co., Ltd.

Kohji Hosokawa

Masatoshi Ishii

Takeo Yasuda

Junka Okazawa

Chung H Lam

Atsuya Okazaki

Yutaka Nakamura

Seiji Munetoh

Takayuki Osogami

SangBum Kim

Devendra K Sadana

Ghavam G Shahidi

Vijay Narayanan

Daniel Joseph Friedman

Dirk Pfeiffer

Ramachandran Muralidhar

Eduard Albert Cartier

Frank Robert Libsch

Robert L Wisnieff

Richard Harold Boivie

Charanjit Singh Jutla

Scott C Lewis

Wanki Kim

Chandrasekara Kothandaraman

Akiyo Iwashina

Lawrence Alfred Clevenger

Nicholas Anthony Lanzillo

Geoffrey W Burr

Toshio Sunaga

Biswanath Senapati

Yohtaroh Mori

Hisatada Miyatake

Shinpei Watanabe

An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.

Buried metal signal rail for memory arrays

A global clock signal distribution system includes a distribution line that includes gates for signal distribution, a function block gate with at least two input ports and a duty compensation gate with at least two input ports. The duty compensation gate is inserted in the distribution line following the function block gate for balancing rise-to-fall delay and fall-to-rise delay. The duty compensation gate delays an earlier arrived edge of the clock signal more than a later arrived edge of the clock signal to compensate delay unbalance.

Duty compensation scheme

A synapse memory and a method for reading a weight value stored in a synapse memory are provided. The synapse memory includes a memory device configured to store a weight value. The memory device includes a read terminal, a write terminal, and a common terminal, the read terminal being configured to receive a read signal, the write terminal being configured to receive a write signal, and the common terminal being configured to output an output signal from the memory device. The synapse memory also includes a write transistor provided between the write terminal of the memory device and a write signal line configured to send the write signal. The synapse memory further includes a common transistor provided between the common terminal of the memory device and one of the dendrite lines.

Synapse memory

A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.

Memory cell in wafer backside

A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.

Performance and area efficient synapse memory cell structure

A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.

Neuromorphic chip for updating precise synaptic weight values

A spiking neural network device including a spiking neural network circuit including a crossbar array of plural synapses; plural axons connected with the spiking neural network circuit, the plural axons receiving input of a spike signal; and plural Poisson spike generators respectively provided for the plural axons. Each Poisson spike generator can be set whether or not to emit the spike signal based on an input signal to be processed, and each Poisson spike generator can, be set to emit the spike signal being configured to generate a Poisson spike train different from each other. and supply the Poisson spike train to a corresponding one of the plural axons.

On-chip Poisson spike generation

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

A neuromorphic synapse array is provided which ensures that a neuron model as such McCulloch-Pitts is dependent on nonlinearity with a single polarity weight cell. The neuromorphic synapse array includes a plurality of synaptic array cells, a plurality of operation column arrays, and a reference column array. The synaptic array cells respectively have a single polarity synapse weight and are classified into operation synapse cells and reference synapse cells for shifting a product-sum of the operation synapse cells. The operation column arrays are defined by the operation synapse cells aligned in column of the array. The reference column array is defined by the reference synapse cells aligned in column of the array.

Weight shifting for neuromorphic synapse array

A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Monitoring potential of neuron circuits

Methods and systems are provided for operating a neuromorphic system for generating neuron and synapse activities. The method includes: preparing at least one digital timer in the neuromorphic system, each of the at least one digital timers including multi-bit digital values; generating time signals using the at least one digital timer; emulating an analog waveform of a neuron spike; updating parameters of the neuromorphic system using the time signals and the current values of the parameters; presetting, using a processor, the digital values of the at least one digital timer to initial values when the spike input is provided to the node; and updating, using the processor, the digital values of the at least one digital timer with a specified amount when there is an absence of a spike input to the node.

Timing sequence for digital STDP synapse and LIF neuron-based neuromorphic system

Encryption engine with an undetectable/tamper proof private key in late node CMOS technology

A method and system are provided for updating synapse weight values in neuromorphic system with Spike Time Dependent Plasticity model. The method includes selectively performing, by a hardware-based synapse weight incrementer or decrementer, one of a synapse weight increment function or decrement function, each using a respective lookup table, to generate updated synapse weight values responsive to spike timing data. The method further includes storing the updated synapse weight values in a memory. The method additionally includes performing, by a hardware-based processor, a learning process to integrate the updated synapse weight values stored in the memory into the Spike Time Dependent Plasticity model neuromorphic system for improved neuromorphic simulation.

LUT based synapse weight update scheme in STDP neuromorphic systems

A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

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Kawasaki, Japan

Kohji Hosokawa