Nippon Steel Corporation

Waseda University

Nippon Steel Materials Co., Ltd.

Texas Instruments Corporation

Nippon Micrometal Corporation

Other

Nippon Steel Sumitomo Metal Corporation

Mitsui High-tec Incorporated

Ball Semiconductor Corporation

Nippon Steel & Sumikin Materials Co., Ltd.

Kohei Tatsumi

Eiji Hashino

Kenji Shimokawa

Tomohiro Uno

Hiroyuki Kondo

Shinichi Terashima

Masashi Konda

Hiroshi Hoshiba

Yoji Kawakami

Takashi Yamada

Daizo Oda

Shinji Ishikawa

Nobuo Takeda

Atsuyuki Fukano

Ryoichi Suzuki

Koji Shimizu

Yasunori Tanaka

Tatsuo Fujimoto

Noboru Ohtani

Masashi Nakabayashi

Masamoto Tanaka

Hiroshi Tsuge

Hirokatsu Yashiro

Masakazu Katsuno

Masao Kimura

Kazutoshi Ueda

Michio Nitta

Atsuo Ikeda

Taizo Hoshino

Shinya Nariki

Toru Bando

Kiyoshi Onodera

Norie Matsubara

Nobuaki Sato

Housei Hirano

Soichi Kadoguchi

A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles(aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chipand a substrateto be bonded to the semiconductor chip, and the metal particlesare fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chipand/or the surface of the substrate

Semiconductor element bonding structure, method for producing semiconductor element bonding structure, and electrically conductive bonding agent

A power semiconductor module device includes: a plurality of semiconductor elements that are arranged at intervals and flush with each other on a plane; an insulating support that fixes the semiconductor elements; a first thick-film plating layer that is formed as a first-surface-side electrode that electrically connects the semiconductor elements to each other on at least one surface of a front surface side and a rear surface side. The first thick-film plating layer supports the semiconductor elements from at least one of an upper direction and a lower direction.

Power semiconductor module device

[Problem] To provide an electrode connection structure and the like in which a plurality of elongated leads are arranged in parallel and a longitudinal side surface of each lead is connected to an electrode by plating treatment with high quality. [Solution] An electrode connection structure in which a semiconductor chipelectrode and/or a substrate electrode is connected to a plurality of elongated leadsof a lead frameby plating. The plurality of elongated leadsof the lead frameare arranged in parallel, and a longitudinal side surface of each leadis connected to the semiconductor chipelectrode and/or the substrate electrode by plating. At a connection portion of a first connection surfaceof the semiconductor chipelectrode and/or the substrate electrode, the first connection surfacebeing connected to the leads, and a second connection surfacein the longitudinal side surface of each lead, the second connection surfacebeing connected to the first connection surface, a distance between the first connection surfaceand the second connection surfacecontinuously increases from an edge portionof the second connection surface, the edge portionbeing in contact with the first connection surface, toward an outer portionof the second connection surface

Electrode connection structure, lead frame, and method for forming electrode connection structure

The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers () including metal nanoparticles to sandwich metal foil () so as to form a joining layer and joining the same type or different types of surface metals (-) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.

Metal joining structure using metal nanoparticles and metal joining method and metal joining material

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

Electrode connection structure and electrode connection method

It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode) on a power semiconductor dieand another metal electrode (connection electrode) are connected by metal wireusing wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 &#x3bc;m and not greater than 2 mm and the diehas thereon one or more metal and/or alloy layers, each of the layer(s) being 50 &#x212b; or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al.

Power semiconductor device, method of manufacturing the device and bonding wire

The periphery of a mask () is formed higher than a region where a ball holding hole () is formed, a work () is arranged at a lower section of the ball holding hole () of the mask (), and the ball holding hole () and an electrode of the work () are aligned with each other. A ball (B) is applied on the mask (), and in such state, vibration is applied to the mask () to move the solder ball (B) on the surface of the mask () and drop the solder ball (B) into the ball holding hole (). The periphery of the mask () is permitted to be lower than the ball holding hole (), and an excessive portion of the solder ball (B) is recovered from over the mask ().

Solder ball mounting method and apparatus

There is provided a bonding wire which does not cause a leaning failure or the like. A semiconductor mounting bonding wire has a breaking elongation of 7 to 20%, and stress at 1% elongation is greater than or equal to 90% of a tensile strength and is less than or equal to 100% thereof.

Semiconductor mounting bonding wire

The invention provides a high-quality SiC single-crystal substrate, a seed crystal for producing the high-quality SiC single-crystal substrate, and a method of producing the high-quality SiC single-crystal substrate, which enable improvement of device yield and stability. Provided is an SiC single-crystal substrate wherein, when the SiC single-crystal substrate is divided into 5-mm square regions, such regions in which dislocation pairs or dislocation rows having intervals between their dislocation end positions of 5 &#x3bc;m or less are present among the dislocations that have ends at the substrate surface account for 50% or less of all such regions within the substrate surface and the dislocation density in the substrate of dislocations other than the dislocation pairs or dislocation is 8,000/cm.

SiC single-crystal substrate and method of producing SiC single-crystal substrate

A bonding wire for a semiconductor device has a core wire and a periphery comprising a conductive metal mainly composed of an element common to both and/or an alloy or alloys of said metal and, between the core wire and the periphery, a diffusion layer or an intermetallic compound layer composed of the elements constituting the core wire and the periphery and a bonding wire for a semiconductor device characterized by having a core wire comprising a first conductive metal or an alloy mainly composed of the first conductive metal, a periphery comprising a second conductive metal different from the first conductive metal of the core wire or an alloy mainly composed of the second conductive metal, and, between the core wire and the periphery, a diffusion layer or an intermetallic compound layer and a method of producing the same.

Bonding wire for semiconductor device and method for producing the same

Gold bonding wires for semiconductor devices featuring increased strength and modulus of elasticity, stable loop shapes, suppressing the flow of wires, suppressing the leaning, and totally improved junctions of the wedge junction portions or wear characteristics for realizing a narrow-pitch connection, and enhanced the productivity on an industrial scale, and a method of producing the same. A gold bonding wire for a semiconductor device has a crystal grain structure in cross section in the lengthwise direction of the bonding wire, wherein a ratio of the area of crystal grains having an orientation [111] to the area of crystal grains having an orientation [100] is not smaller than 1.2 in the crystal orientations in the lengthwise direction of the wire.

Gold bonding wires for semiconductor devices and method of producing the wires

Balls are sucked onto a carrier board so as to be temporarily arranged in a ball arrangement region of the board, and then the balls are transferred and bonded onto an objective substance with their positions being adjusted. Gas blow is applied to the temporarily arranged balls or alternatively the temporarily arranged balls are sucked, so as to remove excess balls other than balls that have been exactly sucked onto the ball arrangement region. Cooperation with application of fine vibration to the carrier board makes the removal of the excess balls more efficient.

Ball transferring method and apparatus

A semiconductor device () comprising electrodes formed on a semiconductor chip () and bumps () which consist of a low melting point metal ball spherically formed and having a given size and which are adhesive bonded to the electrodes (). The electrodes () are formed from an electrode material of Cu or a Cu alloy, Al or an Al alloy, or Au or a Au alloy. When the electrode material is composed of Al or an Al alloy, the electrodes contain, on the electrode material layer of Al or an Al alloy, at least one layer () composed of a metal or metal alloy (preferably a metal selected form Ti, W, Ni, Cr, Au, Pd, Cu, Pt, Ag, Sn or Pb, or an alloy of these metals) having a melting point higher than the electrode material. The low melting point metal balls () are adhesive bonded to the electrodes () preferably with a flux. The low melting point metal balls () adhesive bonded to the respective electrodes () may also be reflowed to form semispherical bumps () before use.

Method for fabricating a semiconductor devices provided with low melting point metal bumps

Semiconductor device provided with low melting point metal bumps

Growing community of inventors

Tokyo, Japan

Kohei Tatsumi