Japan Science and Technology Agency

Kyushu Institute of Technology

System Jd Co., Ltd.

Lptex Corporation

Kyushu University

Kohei Miyase

Seiji Kajihara

Xiaoqing Wen

Hiroshi Date

Yoshihiro Minamoto

Yasuo Sato

Senling Wang

Yuta Yamato

Xiaqing Wen

The purpose of the invention is to provide a fault detection system etc., that reduces shift power in scan-out while maintaining the fault coverage. The fault detection system configured to detect a fault in a logic circuit by means of a scan test, includes: multiple flip-flops; a final signal generation unit that generates a final signal indicating a final capture in a capture mode; an assignment unit that differs from the logic circuit and the flip-flops, and that sets a logic signal for a part of the flip-flops upon receiving the final signal; and a fault detection device that detects a fault by making a comparison between a test output captured from the logic circuit and including the logic value set by the assignment unit and a test output to be obtained when the logic circuit has no fault and including the logic value set by the assignment unit.

Fault detection system, generation circuit, and program

The provided are a don't-care-bit identification method and program for identifying don't-care-bits from the first and the second input vectors in an input-vector pair while keeping the sensitization status of paths, in a combinational circuit, sensitized by applying the first and the second input vectors in serial to input lines of combinational circuit. The method identifies an unspecified bit from the first and the second input vectors Vand Vcomposed of logic values 0 and 1, which are applied to the combinational portion in a sequential circuit or to an independent combinational circuit. The method includes an identification step for identifying an unspecified bit from the first and the second input vectors, while keeping sensitization status of a part of or all of the paths, sensitized by applying the first and the second input vectors.

Don't-care-bit identification method and don't-care-bit identification program

Logic value determination method and program for identifying unspecified bits and determining logic values shortly. The method enables to control the total number of logic value differences between corresponding input and output lines of combinational circuit. The method includes the first step for determining, when output has a logic value and input has an unspecified value, that the unspecified bit has the logic value of output, the second step for determining, when output has an unspecified value and input has a logic value, the logic value of the unspecified bit by justification, and the third step for calculating, when input and output both have unspecified values, probabilities of output to have 0 and 1, and determining the logic value of the unspecified bit based on the difference between the probabilities. The third step is repeated until the total number reaches a target value.

Target logic value determination method for unspecified bit in test vector for combinational circuit and non-transitory computer-readable medium

Provided are a generation device to reduce launch switching activity, yield loss risk, and power consumption of testing, even in the at-speed scan testing, even with a small number of don't-care (X) bits in input bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design, by putting focus on internal lines in the circuit. The generation device includes a target internal line selection unit, a target internal line distinction unit, an identification unit that identifies a bit to be an unspecified bit and a bit to be a logic bit in the input bits, and an assignment unit that assigns a logic value 1 or a logic value 0 to unspecified bits in the input bits. The identification unit includes an unspecified bit identification unit and an input logic bit identification unit.

Generating device, generating method, and program

Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test patterngiven in advance for a logic circuit into an intermediate test patternof a bit constitution of different logic values, where the constitution elements of the initial test patternare at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test patternwhich meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.

Conversion device, conversion method, program, and recording medium

A test pattern generation method for determining if a combinational portionis defective, by applying test patterns to a semiconductor integrated circuitand comparing responses to the test patterns with expected responses, the method including: a first step of generating test patterns having logic bits for detecting defects and unspecified bits; a second step of selecting critical pathsgenerated by the application of the test patterns; a third step of identifying critical gates on the critical paths; and a fourth step of determining unspecified bits so that a critical capture transition metric, which indicates the number of the critical gates whose states are changed, is reduced; wherein by reducing the critical capture transition metric, output delays from the critical pathsare prevented, and thereby false testing can be avoided.

Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit

Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation devicegenerates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube. The generation deviceincludes a selection unitfor selecting, among the plurality of X-bits, a target X-bit, which is a target of assigning a logic value, a capture transition metric calculation unitfor calculating capture transition metric caused by a test cube including an X-bit, and a logic value assignment unitfor assigning, to the selected target X-bit, a logic value which causes the smaller capture transition metric, by applying the capture transition metric calculation means to a first test cube obtained by assigning a logic value 0 to the selected target X-bit and to a second test cube obtained by assigning a logic value 1 to the selected target X-bit, and by comparing a capture transition metric caused by a first test cube and a capture transition metric caused by a second test cube.

Generating device, generating method, program and recording medium

Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vector set corresponding to the full scan sequential circuit. The conversion device comprises a setting unit for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit.

A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatusgenerating an initial test vector setfor a logic circuit includes a target vector identification unitidentifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set, and a test vector set conversion unitconverting the test vector identified by the test vector identification unitand to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.

Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic devicehas a symbol injection part, which is composed of a symbol injection part for an active elementand a symbol injection part for a passive element, an occurrence probability providing part, an equal occurrence probability providing part, and a switching part. A per-test X-fault diagnosis flow by the diagnostic deviceconsists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution. Since, by the occurrence probability providing part, a new diagnosis value is used and, the occurrence probabilities of possible faulty logic combinations are taken into consideration, the reality in a deep-submicron LSI circuit is better reflected, which contributes to the improvement of diagnostic resolution.

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Fukuoka, Japan

Kohei Miyase