Sony Corporation

Kohei Kudo

Yasuhide Shimizu

Shigemitsu Murayama

Hiroaki Yatsuda

Shinichiro Eto

Disclosed herein is an analog to digital converter including an analog to digital conversion stage of at least one stage adapted to produce digital data of a value corresponding to a relationship to two analog signals inputted thereto and output two analog residual signals. The analog to digital conversion stage includes a signal production section, a comparison section, a first outputting section, a second outputting section, and a changeover section. The comparison section outputs first digital data when a first comparison result that the voltage value of the first analog signal is lower than the voltage value of the second analog signal is obtained whereas the comparison section outputs second digital data when a second comparison result that the voltage value of the first analog signal is higher than the voltage value of the second analog signal is obtained.

Analog to digital converter and signal processing system

An analog to digital converter includes: a reference circuit adapted to generate reference voltages; differential amplifiers; normal phase circuits each of which samples a normal phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a first input terminal of one of the differential amplifiers when the input is differential and single-ended; and reversed phase circuits each of which samples a reversed phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a second input terminal of one of the differential amplifiers when the input is differential and which samples a ground level as a reference voltage of the reference circuit and supplies the reference voltage and comparison voltage to the second input terminal of the differential amplifier when the input is single-ended.

A/D converter

A parallel type analog-to-digital conversion circuit, including a reference signal generating portion and a comparison amplification portion, the comparison amplification portion including a plurality of amplifiers, input resetting switches, first sampling capacitors, second sampling capacitors, first sampling switches, and second sampling switches.

Parallel type analog-to-digital conversion circuit, sampling circuit and comparison amplification circuit

A serial-parallel type analog-to-digital converter includes a reference voltage generator, a higher bit comparing portion and a lower bit comparing portion, and a reference voltage selecting portion, wherein the lower bit comparing portion includes the plurality of comparison stages.

Serial-parallel type analog-to-digital converter and analog-to-digital conversion method

A subranging analog-to-digital converter is disclosed. The converter includes: a divided voltage generation circuit that equally divides a range of a predetermined voltage, and generates 2+1 divided voltages; a higher-order conversion circuit that generates a signal for higher-order m bits of the digital signal by comparing the analog signal with the 2&#x2212;1 or less of the 2+1 divided voltages; a switch circuit that selects at least two of the 2+1 divided voltages based on information provided by the higher-order conversion circuit; a lower-order conversion circuit that generates a signal for lower-order n bits (n=N&#x2212;m) of the digital signal by comparing the analog signal with the divided voltages being a selection result of the switch circuit; and an encoder that generates the digital signal based on the signal provided by the higher-order conversion circuit and the signal provided by the lower-order conversion circuit.

Subranging converter for converting an analog signal into an N-bit digital signal

A semiconductor device includes a semiconductor substrate and a ladder resistor formed on the semiconductor substrate. The ladder resistor includes a plurality of elongated resistor portions arranged in parallel with each other, a plurality of connection portions that connect the resistor portions at predetermined intervals in a longitudinal direction of the resistor portions, and a plurality of voltage extraction portions provided in order to extract voltages at the individual connection portions.

Growing community of inventors

Nagasaki, Japan

Kohei Kudo